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1. 发明申请

US20080094882A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20080094882A1
公开(公告)日：2008-04-24
申请号：US11876607
申请日：2007-10-22
申请人： Hideo Asano , Koji Kitamura , Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki
发明人： Hideo Asano , Koji Kitamura , Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.
摘要翻译：根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管; 其中所述存储器单元中的至少一些被布置成二维阵列; 第一互连线，沿着所述存储器阵列的第一方向延伸并且用作包含在每个存储单元中的选择晶体管的栅电极; 在存储器阵列的第一方向上延伸的第二互连线; 第三互连线，沿第二方向延伸; 其中所述存储器单元中的至少一些的所述磁阻元件夹在所述第二和第三互连线之间，其中所述第二互连线至少部分地沿着所述存储器单元中的特定一个的所有磁阻元件延伸。

2. 发明授权

US07313045B2 Dynamic semiconductor storage device 失效
标题翻译：动态半导体存储设备
公开(公告)号：US07313045B2
公开(公告)日：2007-12-25
申请号：US10553578
申请日：2004-04-13
申请人： Kohji Hosokawa , Hisatada Miyatake , Toshio Sunaga
发明人： Kohji Hosokawa , Hisatada Miyatake , Toshio Sunaga
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by selectively setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.
摘要翻译：为了通过简单的电路配置来实现通过选择性地设置刷新周期来有效地降低刷新电流的DRAM。存储单元阵列被分成64个子阵列，每个子阵列进一步分成8个块。刷新周期控制电路具有用于设定分频比为1或1/2的熔丝电路，分频器，其将预解码信号的频率除以设定的分频比，用于设定分频比为1的熔丝电路或1/4，以及用于将预解码信号除以设定分频比的分频器。刷新周期控制电路能够为64个子阵列设置64 ms或128 ms的刷新周期，512个块的64 ms或256 ms刷新周期。

3. 发明申请

US20060227600A1 Non-Volatile Memory Device 失效
标题翻译：非易失性存储器件
公开(公告)号：US20060227600A1
公开(公告)日：2006-10-12
申请号：US11381578
申请日：2006-05-04
申请人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
发明人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines
摘要翻译：根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管，其中存储单元被布置成二维阵列。第一互连线在存储器阵列的第一方向上延伸，并且用作包含在每个存储单元中的选择晶体管的栅电极。第二互连线在存储器阵列的第一方向上延伸。第三互连线在第二方向上延伸。至少一些存储单元的磁电阻元件夹在第二和第三互连线之间

4. 发明申请

US20050141143A1 Magnetic head of magnetoresistance effect type and process for production thereof 失效
标题翻译：磁阻效应磁头及其制造方法
公开(公告)号：US20050141143A1
公开(公告)日：2005-06-30
申请号：US11009773
申请日：2004-12-10
申请人： Hiroyuki Ono , Hiroaki Suzuki , Toshio Sunaga , Hisatada Miyatake , Hideo Asano
发明人： Hiroyuki Ono , Hiroaki Suzuki , Toshio Sunaga , Hisatada Miyatake , Hideo Asano
IPC分类号： G11B5/39 , G11B5/127 , G11B5/33 , G11B5/40 , H01L43/08
CPC分类号： G11B5/39
摘要： In the case of magnetic head of magnetoresistance effect type whose breakdown voltage is as low as 0.3 V, it is impractical to ignore even a very small amount of static electricity that occurs during fabrication or use. In one embodiment, the desired magnetic head is produced by forming an SiO2 layer on a silicon slider, thereby forming an SOI substrate; forming on the SOI substrate circuits to protect a TMR element from overvoltage and a read-write circuit; forming field effect transistors from an Si semiconductor layer (formed by reduction of the SiO2 layer or epitaxial growth on the SiO2 layer); forming three electrodes (source, gate, drain) on the Si semiconductor layer; forming a Schottky diode by Schottky contact (metal) with the Si semiconductor layer; forming overvoltage protective circuits of aluminum wiring on the SOI substrate; and forming a TMR element.
摘要翻译：在其击穿电压低至0.3V的磁阻效应型磁头的情况下，即使在制造或使用期间发生的非常少量静电也是不切实际的。在一个实施例中，通过在硅滑块上形成SiO 2层来形成所需的磁头，由此形成SOI衬底; 在SOI衬底电路上形成以保护TMR元件免受过电压和读写电路; 从Si半导体层（通过SiO 2层的还原或SiO 2层上的外延生长形成）形成场效应晶体管; 在Si半导体层上形成三个电极（源极，栅极，漏极）; 通过与Si半导体层的肖特基接触（金属）形成肖特基二极管; 在SOI衬底上形成铝布线的过电压保护电路; 并形成TMR元件。

5. 发明授权

US07511981B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07511981B2
公开(公告)日：2009-03-31
申请号：US11876607
申请日：2007-10-22
申请人： Hideo Asano , Koji Kitamura , Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki
发明人： Hideo Asano , Koji Kitamura , Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki
IPC分类号： G11C5/08
CPC分类号： G11C11/16
摘要： A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.
摘要翻译：根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管; 其中所述存储器单元中的至少一些被布置成二维阵列; 第一互连线，沿着所述存储器阵列的第一方向延伸并且用作包含在每个存储单元中的选择晶体管的栅电极; 在存储器阵列的第一方向上延伸的第二互连线; 第三互连线，沿第二方向延伸; 其中所述存储器单元中的至少一些的所述磁阻元件夹在所述第二和第三互连线之间，其中所述第二互连线至少部分地沿着所述存储器单元中的特定一个的所有磁阻元件延伸。

6. 发明申请

US20080291746A1 Semiconductor Storage Device and Burst Operation Method 审中-公开
标题翻译：半导体存储设备和突发操作方法
公开(公告)号：US20080291746A1
公开(公告)日：2008-11-27
申请号：US10595742
申请日：2004-11-04
申请人： Toshio Sunaga , Kohji Hosokawa , Hisatada Miyatake , Yutaka Nakamura
发明人： Toshio Sunaga , Kohji Hosokawa , Hisatada Miyatake , Yutaka Nakamura
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/4076 , G11C7/08 , G11C7/1018 , G11C11/4096
摘要： The present invention is a PSRAM in which a burst length can be increased without increasing consumed current, and a burst operation method therefor. In operation, column selection lines CSL1 and CSL2 are driven in order during activation of sense amplifiers. This causes bit switches BSW1-BSW8 to be turned on in units of four bit switches and then 8-bit read data RD is latched from bit line pairs BL1-BL8 into prefetch/preload latches PFPLL1-PFPLL8 in units of 4-bits. The 8-bit read data RD is continuously output to a single data I/O bus I/O1 in units of one bit and in order.
摘要翻译：本发明是一种PSRAM，其中可以增加突发长度而不增加消耗电流，以及其突发操作方法。在操作中，列选择线CSL1和CSL2在感测放大器的激活期间按顺序驱动。这使得位开关BSW1-BSW8以四位开关为单位接通，然后8位读数据RD从位线对BL1-BL8以4位为单位锁存到预取/预加载锁存器PFPLL1-PFPLL8中。 8位读数据RD以1位为单位连续输出到单个数据I / O总线I / O1。

7. 发明授权

US06992924B2 Magnetic memory and method for optimizing write current in a magnetic memory 有权
标题翻译：磁存储器和用于优化磁存储器中的写入电流的方法
公开(公告)号：US06992924B2
公开(公告)日：2006-01-31
申请号：US10680051
申请日：2003-10-07
申请人： Hisatada Miyatake , Hiroshi Umezaki , Kohji Kitamura , Toshio Sunaga , Kohki Noda , Hideo Asano
发明人： Hisatada Miyatake , Hiroshi Umezaki , Kohji Kitamura , Toshio Sunaga , Kohki Noda , Hideo Asano
IPC分类号： G11C11/15
CPC分类号： G11C11/16 , G11C29/02 , G11C29/028 , G11C2029/5006
摘要： The invention provides methods and apparatus for for determining and providing optimum write bit line current and write word line current in an MRAM. A single reference potential is used to determine the values of the write line current and the bit line current. In determining the optimal values, asteroid curves representing bit line magnetic fields Hx generated by write bit line current IB and word line magnetic fields Hy generated by write word line current Iw for magnetization are considered, and an asteroid curve ACout is defined outside the asteroid curves of all memory cells taking manufacture variations and design margins into account. A write bit line current and a write word line current are selected such that the write current obtained by adding the write bit line current or currents and the write word line current, or the write power consumed by the bit line or lines and the write word line is minimized. Furthermore, in order to prevent multi-selection, the write bit line current and the write word line current are selected so that they generate a synthetic magnetic field on the curve between calculated points of the asteroid curve ACout.
摘要翻译：本发明提供了用于在MRAM中确定和提供最佳写入位线电流和写入字线电流的方法和装置。单个参考电位用于确定写入线电流和位线电流的值。在确定最佳值时，表示通过写入位线电流I B和字线磁场H SUB生成的位线磁场H 的小行星曲线考虑了用于磁化的写入字线电流I 产生的小行星曲线AC＆lt; SUB＆gt;被定义在所有存储器单元的小行星曲线之外，其采取制造变化和设计余量考虑到选择写位线电流和写字线电流，使得通过将写位线电流或电流和写字线电流相加而获得的写入电流或由位线或线消耗的写入功率和写入字线最小化。此外，为了防止多次选择，选择写入位线电流和写入字线电流，使得它们在小行星曲线AC的计算点之间的曲线上产生合成磁场，。

8. 发明授权

US07522458B2 Memory and method of controlling access to memory 失效
标题翻译：控制内存访问的内存和方法
公开(公告)号：US07522458B2
公开(公告)日：2009-04-21
申请号：US11535703
申请日：2006-09-27
申请人： Toshio Sunaga , Hisatada Miyatake
发明人： Toshio Sunaga , Hisatada Miyatake
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40615 , G11C11/4076
摘要： A memory including at least one memory cell array and an access control circuit for controlling access to the memory array. The access control circuit includes an access command circuit (ADRCTL) that receives a first (CE) and a second (ADV) input signals and outputs an access command signal (ACMDS) enabling commencement of memory access, and a command discriminating circuit (CMDDEC) that receives the first (CE) and second (ADV) input signals, a third (OE) and a fourth (WE) input signals, and a clock signal (CLK), and that outputs a command discriminating signal (WRITE) for specifying whether the access command signal is for a read operation or a write operation.
摘要翻译：存储器，包括至少一个存储单元阵列和用于控制对存储器阵列的访问的访问控制电路。访问控制电路包括接收第一（CE）和第二（ADV）输入信号的访问命令电路（ADRCTL），并且输出允许开始存储器访问的访问命令信号（ACMDS）和命令识别电路（CMDDEC）接收第一（CE）和第二（ADV）输入信号，第三（OE）和第四（WE）输入信号以及时钟信号（CLK）），并输出指令判别信号（WRITE）访问命令信号用于读取操作或写入操作。

9. 发明授权

US07349235B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US07349235B2
公开(公告)日：2008-03-25
申请号：US11381578
申请日：2006-05-04
申请人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
发明人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
IPC分类号： G11C5/08
CPC分类号： G11C11/16
摘要： A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines.
摘要翻译：根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管，其中存储单元被布置成二维阵列。第一互连线在存储器阵列的第一方向上延伸，并且用作包含在每个存储单元中的选择晶体管的栅电极。第二互连线在存储器阵列的第一方向上延伸。第三互连线在第二方向上延伸。至少一些存储单元的磁电阻元件夹在第二和第三互连线之间。

10. 发明申请

US20050073897A1 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US20050073897A1
公开(公告)日：2005-04-07
申请号：US10964352
申请日：2004-10-12
申请人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
发明人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/16
摘要： MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.
摘要翻译： MRAM具有在y方向上延伸的字线WLR和写入字线WLW，在x方向上延伸的写入/读取位线BLW / R和写入位线BLW，以及设置在这些交点处的存储单元MC 线条。存储器MC包括子单元SC1和SC2。子单元SC1包括磁阻元件MTJ1和MTJ2以及选择晶体管Tr1，子单元SC2包括磁阻元件MTJ3和MTJ4以及选择晶体管Tr2。磁电阻元件MTJ1和MTJ2并联连接，磁电阻元件MTJ3和MTJ4也并联连接。此外，子单元SC1和SC2串联连接在写/读位线BLW / R和地之间。

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