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1. 发明授权

US06826076B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US06826076B2
公开(公告)日：2004-11-30
申请号：US10057369
申请日：2002-01-24
申请人： Hideo Asano , Koji Kitamura , Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki
发明人： Hideo Asano , Koji Kitamura , Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.
摘要翻译： MRAM具有在y方向上延伸的字线WLR和写入字线WLW，在x方向上延伸的写入/读取位线BLW / R和写入位线BLW，以及设置在这些交点处的存储单元MC 线条。存储器MC包括子单元SC1和SC2。子单元SC1包括磁阻元件MTJ1和MTJ2以及选择晶体管Tr1，子单元SC2包括磁阻元件MTJ3和MTJ4以及选择晶体管Tr2。磁电阻元件MTJ1和MTJ2并联连接，磁电阻元件MTJ3和MTJ4也并联连接。此外，子单元SC1和SC2串联连接在写/读位线BLW / R和地之间。

2. 发明授权

US07511981B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07511981B2
公开(公告)日：2009-03-31
申请号：US11876607
申请日：2007-10-22
申请人： Hideo Asano , Koji Kitamura , Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki
发明人： Hideo Asano , Koji Kitamura , Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki
IPC分类号： G11C5/08
CPC分类号： G11C11/16
摘要： A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.
摘要翻译：根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管; 其中所述存储器单元中的至少一些被布置成二维阵列; 第一互连线，沿着所述存储器阵列的第一方向延伸并且用作包含在每个存储单元中的选择晶体管的栅电极; 在存储器阵列的第一方向上延伸的第二互连线; 第三互连线，沿第二方向延伸; 其中所述存储器单元中的至少一些的所述磁阻元件夹在所述第二和第三互连线之间，其中所述第二互连线至少部分地沿着所述存储器单元中的特定一个的所有磁阻元件延伸。

3. 发明授权

US07349235B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US07349235B2
公开(公告)日：2008-03-25
申请号：US11381578
申请日：2006-05-04
申请人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
发明人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
IPC分类号： G11C5/08
CPC分类号： G11C11/16
摘要： A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines.
摘要翻译：根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管，其中存储单元被布置成二维阵列。第一互连线在存储器阵列的第一方向上延伸，并且用作包含在每个存储单元中的选择晶体管的栅电极。第二互连线在存储器阵列的第一方向上延伸。第三互连线在第二方向上延伸。至少一些存储单元的磁电阻元件夹在第二和第三互连线之间。

4. 发明申请

US20050073897A1 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US20050073897A1
公开(公告)日：2005-04-07
申请号：US10964352
申请日：2004-10-12
申请人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
发明人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/16
摘要： MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.
摘要翻译： MRAM具有在y方向上延伸的字线WLR和写入字线WLW，在x方向上延伸的写入/读取位线BLW / R和写入位线BLW，以及设置在这些交点处的存储单元MC 线条。存储器MC包括子单元SC1和SC2。子单元SC1包括磁阻元件MTJ1和MTJ2以及选择晶体管Tr1，子单元SC2包括磁阻元件MTJ3和MTJ4以及选择晶体管Tr2。磁电阻元件MTJ1和MTJ2并联连接，磁电阻元件MTJ3和MTJ4也并联连接。此外，子单元SC1和SC2串联连接在写/读位线BLW / R和地之间。

5. 发明授权

US06785154B2 MRAM and access method thereof 有权
标题翻译： MRAM及其访问方法
公开(公告)号：US06785154B2
公开(公告)日：2004-08-31
申请号：US10134100
申请日：2002-04-26
申请人： Toshio Sunaga , Hisatada Miyatake , Koji Kitamura , Hideo Asano , Kohki Noda , Hiroshi Umezaki
发明人： Toshio Sunaga , Hisatada Miyatake , Koji Kitamura , Hideo Asano , Kohki Noda , Hiroshi Umezaki
IPC分类号： G11C1700
CPC分类号： G11C11/15 , G11C2207/2263
摘要： A magnetic random access memory (MRAM) circuit block and access method thereof are disclosed herein which includes a circuit for sensing a data write current passing through a bitline 32 and, for generating a stop signal for stopping a data write current supply to the bitline 32 and a write wordline 30 after data is written in an magnetic tunnel junction (MTJ) element 44. Further, when data to be written to the storage element is the same as the data already stored therein, no write current is supplied to the write wordline 30, thereby saving power.
摘要翻译：本文公开了磁性随机存取存储器（MRAM）电路块及其访问方法，其包括用于感测通过位线32的数据写入电流的电路，并且用于产生用于停止向位线32的数据写入电流供应的停止信号以及数据写入磁性隧道结（MTJ）元件44之后的写入字线30.此外，当要写入存储元件的数据与已经存储的数据相同时，不向写入字线提供写入电流 30，从而节省电力。

6. 发明授权

US07123498B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US07123498B2
公开(公告)日：2006-10-17
申请号：US10964352
申请日：2004-10-12
申请人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
发明人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
IPC分类号： G11C5/06
CPC分类号： G11C11/16
摘要： MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.
摘要翻译： MRAM具有在y方向上延伸的字线WLR和写入字线WLW，在x方向上延伸的写入/读取位线BLW / R和写入位线BLW，以及设置在这些交点处的存储单元MC 线条。存储器MC包括子单元SC 1和SC 2。子单元SC1包括磁电阻元件MTJ 1和MTJ 2以及选择晶体管Tr 1，子单元SC 2包括磁阻元件MTJ 3和MTJ 4以及选择晶体管Tr 2。磁电阻元件MTJ 1和MTJ 2并联连接，磁电阻元件MTJ 3和MTJ 4也并联连接。此外，子单元SC 1和SC 2串联连接在写/读位线BLW / R和地之间。

7. 发明授权

US06639834B2 Data register and access method thereof 有权
公开(公告)号：US06639834B2
公开(公告)日：2003-10-28
申请号：US10134101
申请日：2002-04-26
申请人： Toshio Sunaga , Hisatada Miyatake , Koji Kitamura , Hideo Asano , Kohki Noda , Hiroshi Umezaki
发明人： Toshio Sunaga , Hisatada Miyatake , Koji Kitamura , Hideo Asano , Kohki Noda , Hiroshi Umezaki
IPC分类号： G11C1604
CPC分类号： G11C11/15 , G11C14/0081
摘要： The register disclosed herein includes a register block and a data writing block having non-volatile storage elements which store data output therefrom. The disclosed register further includes a data restoring block for reading data from the non-volatile storage elements. In a disclosed embodiment, the non-volatile storage elements are magnetic tunnel junction (MTJ) elements.

8. 发明申请

US20080094882A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20080094882A1
公开(公告)日：2008-04-24
申请号：US11876607
申请日：2007-10-22
申请人： Hideo Asano , Koji Kitamura , Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki
发明人： Hideo Asano , Koji Kitamura , Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.
摘要翻译：根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管; 其中所述存储器单元中的至少一些被布置成二维阵列; 第一互连线，沿着所述存储器阵列的第一方向延伸并且用作包含在每个存储单元中的选择晶体管的栅电极; 在存储器阵列的第一方向上延伸的第二互连线; 第三互连线，沿第二方向延伸; 其中所述存储器单元中的至少一些的所述磁阻元件夹在所述第二和第三互连线之间，其中所述第二互连线至少部分地沿着所述存储器单元中的特定一个的所有磁阻元件延伸。

9. 发明申请

US20060227600A1 Non-Volatile Memory Device 失效
标题翻译：非易失性存储器件
公开(公告)号：US20060227600A1
公开(公告)日：2006-10-12
申请号：US11381578
申请日：2006-05-04
申请人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
发明人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines
摘要翻译：根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管，其中存储单元被布置成二维阵列。第一互连线在存储器阵列的第一方向上延伸，并且用作包含在每个存储单元中的选择晶体管的栅电极。第二互连线在存储器阵列的第一方向上延伸。第三互连线在第二方向上延伸。至少一些存储单元的磁电阻元件夹在第二和第三互连线之间

10. 发明授权

US07474557B2 MRAM array and access method thereof 有权
公开(公告)号：US07474557B2
公开(公告)日：2009-01-06
申请号：US10134143
申请日：2002-04-26
申请人： Toshio Sunaga , Hisatada Miyatake , Koji Kitamura
发明人： Toshio Sunaga , Hisatada Miyatake , Koji Kitamura
IPC分类号： G11C11/14
CPC分类号： G11C8/14 , G11C11/15
摘要： A magnetic random access memory (MRAM) array is disclosed herein in which a plurality of wordlines and a plurality of bitlines are provided in matrix form, the wordlines including read wordlines and write wordlines, and memory elements are provided at the intersections of the wordlines and the bitlines, memory elements, respectively, including at least a ferromagnetic layer having a magnetization direction determined by the orientation of a magnetic field generated by an electric current passing through the bitline, and a read wordline driver connected to the memory array adapted to provide a first read signal to a first read wordline of a plurality of read wordlines, wherein a second read signal is provided to activate a second read wordline while the first read wordline remains activated.

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