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1. 发明申请

US20110101454A1 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110101454A1
公开(公告)日：2011-05-05
申请号：US12939273
申请日：2010-11-04
申请人： Hisao Ichijo , Alberto Adan
发明人： Hisao Ichijo , Alberto Adan
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816
摘要： A P type semiconductor substrate includes a P type body region, an N type drift region formed away from the P type body region in a direction parallel to a substrate surface, an N type drain region formed in a region separated by a field oxide film in the N type drift region so as to have a concentration higher than the N type drift region, an N type source region formed in the P type body region so as to have a concentration higher than the N type drift region. A P type buried diffusion region having a concentration higher than the N type drift region is formed of a plurality of parts each of which is connected to a part of the bottom surface of the P type body region and extends parallel to the substrate surface and its tip end reaches the inside of the drift region.
摘要翻译： AP型半导体衬底包括P型体区域，在与P基体表面平行的方向上离开P型体区域形成的N型漂移区域，形成在由场氧化膜分离的区域中的N型漏极区域 N型漂移区域以具有高于N型漂移区域的浓度，形成在P型体区域中的浓度高于N型漂移区域的N型源极区域。具有浓度高于N型漂移区域的AP型埋入扩散区域由多个部分形成，每个部分与P型体区域的底表面的一部分连接并且平行于衬底表面延伸并且其尖端末端到达漂移区域的内部。

2. 发明申请

US20090159970A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090159970A1
公开(公告)日：2009-06-25
申请号：US12331470
申请日：2008-12-10
申请人： Hisao Ichijo , Alberto Adan , Kazushi Naruse , Atsushi Kagisawa
发明人： Hisao Ichijo , Alberto Adan , Kazushi Naruse , Atsushi Kagisawa
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66681
摘要： Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area.
摘要翻译：提供一种能够以低成本制造并具有低导通电阻和高耐压的半导体器件及其制造方法。半导体器件包括形成在P型半导体衬底上的N型阱区，在阱区内形成的P型体区，形成在体区内的N型源极区，形成N型漏极区在井区域内与身体区域相隔一定距离处，形成为覆盖体区域的一部分的栅极绝缘膜，形成在栅极绝缘膜上的栅电极和与该绝缘膜接触的P型埋入扩散区域底部，并且在平坦于该区域内的半导体衬底的表面的方向上延伸到漏极区域下方的区域。

3. 发明授权

US08334568B2 Semiconductor device and method for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08334568B2
公开(公告)日：2012-12-18
申请号：US12939273
申请日：2010-11-04
申请人： Hisao Ichijo , Alberto Adan
发明人： Hisao Ichijo , Alberto Adan
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816
摘要： A P type semiconductor substrate includes a P type body region, an N type drift region formed away from the P type body region in a direction parallel to a substrate surface, an N type drain region formed in a region separated by a field oxide film in the N type drift region so as to have a concentration higher than the N type drift region, an N type source region formed in the P type body region so as to have a concentration higher than the N type drift region. A P type buried diffusion region having a concentration higher than the N type drift region is formed of a plurality of parts each of which is connected to a part of the bottom surface of the P type body region and extends parallel to the substrate surface and its tip end reaches the inside of the drift region.
摘要翻译： AP型半导体衬底包括P型体区域，在与P基体表面平行的方向上离开P型体区域形成的N型漂移区域，形成在由场氧化膜分离的区域中的N型漏极区域 N型漂移区域以具有高于N型漂移区域的浓度，形成在P型体区域中的浓度高于N型漂移区域的N型源极区域。具有浓度高于N型漂移区域的AP型埋入扩散区域由多个部分形成，每个部分与P型体区域的底表面的一部分连接并且平行于衬底表面延伸并且其尖端末端到达漂移区域的内部。

4. 发明授权

US08004040B2 Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08004040B2
公开(公告)日：2011-08-23
申请号：US12331470
申请日：2008-12-10
申请人： Hisao Ichijo , Alberto Adan , Kazushi Naruse , Atsushi Kagisawa
发明人： Hisao Ichijo , Alberto Adan , Kazushi Naruse , Atsushi Kagisawa
IPC分类号： H01L29/66
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66681
摘要： Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area.
摘要翻译：提供一种能够以低成本制造并具有低导通电阻和高耐压的半导体器件及其制造方法。半导体器件包括形成在P型半导体衬底上的N型阱区，在阱区内形成的P型体区，形成在体区内的N型源极区，形成N型漏极区在井区域内与身体区域相隔一定距离处，形成为覆盖体区域的一部分的栅极绝缘膜，形成在栅极绝缘膜上的栅电极和与该绝缘膜接触的P型埋入扩散区域底部，并且在平坦于该区域内的半导体衬底的表面的方向上延伸到漏极区域下方的区域。

5. 发明授权

US08143691B2 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08143691B2
公开(公告)日：2012-03-27
申请号：US12585273
申请日：2009-09-10
申请人： Hisao Ichijo
发明人： Hisao Ichijo
IPC分类号： H01L23/58
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/4238 , H01L29/66681
摘要： To provide a semiconductor device and a method of making the same, the device being capable of preventing decrease in the withstanding voltage along the direction perpendicular to the source-drain direction and thereby improving the resistance to an overvoltage (overcurrent), the device includes: a p-type semiconductor substrate 201; an n-type diffusion region 202; a p-type body region 206, a p-type buried diffusion region 204, and an n-type drift region 207 within the n-type diffusion region 202; an n-type source region 208 and a p-type body contact region 209 within the p-type body region 206; an n-type drain region 210 within the n-type drift region 207; a gate insulating film above the p-type body region 206; and a gate electrode 211 above the gate insulating film, where the region 204 extends away from the region 206 farther than the farther edge of the gate electrode 211 is along a cross section perpendicular to the source-drain direction.
摘要翻译：为了提供一种半导体器件及其制造方法，该器件能够防止沿着与源极 - 漏极方向垂直的方向的耐受电压降低，从而提高对过电压（过电流）的抵抗性，该器件包括： p型半导体衬底201; n型扩散区域202; n型扩散区域202内的p型体区域206，p型埋入扩散区域204和n型漂移区域207; p型体区域206内的n型源极区域208和p型体接触区域209; n型漂移区域207内的n型漏极区域210; p型体区域206上方的栅极绝缘膜; 以及栅极绝缘膜上方的栅电极211，其中区域204远离距离栅电极211的更远边缘更远的区域206沿着与源极 - 漏极方向垂直的横截面。

6. 发明授权

US07157772B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07157772B2
公开(公告)日：2007-01-02
申请号：US11167429
申请日：2005-06-28
申请人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
发明人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/7824 , H01L29/402 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/66681
摘要： A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide film is formed such that the thickness of the insulating film at an end-portion region, which is on an end portion of the gate electrode provided to extend over a part of the LOCOS oxide film, as viewed from a main surface of a supporting substrate, is smaller than the thickness of the insulating film below an end portion of the source electrode above the drain region and smaller than the thickness of the insulating film on an end portion of the gate electrode above a body region.
摘要翻译：栅电极的一端延伸到LOCOS氧化膜的一部分上，并且源极电极的一端延伸得比LOCOS氧化膜的一部分上的栅电极的端部更远。形成覆盖栅电极和LOCOS氧化物膜的绝缘膜，使得位于栅电极的端部上的端部区域上的绝缘膜的厚度设置成延伸到LOCOS氧化物膜的一部分上从支撑基板的主表面观察，小于在漏极区域之上的源电极的端部下方的绝缘膜的厚度，并且小于栅电极的端部上的绝缘膜的厚度在身体区域之上。

7. 发明申请

US20060017105A1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060017105A1
公开(公告)日：2006-01-26
申请号：US11167429
申请日：2005-06-28
申请人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
发明人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7824 , H01L29/402 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/66681
摘要： A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide film is formed such that the thickness of the insulating film at an end-portion region, which is on an end portion of the gate electrode provided to extend over a part of the LOCOS oxide film, as viewed from a main surface of a supporting substrate, is smaller than the thickness of the insulating film below an end portion of the source electrode above the drain region and smaller than the thickness of the insulating film on an end portion of the gate electrode above a body region.
摘要翻译：栅电极的一端延伸到LOCOS氧化膜的一部分上，并且源极电极的一端延伸得比LOCOS氧化膜的一部分上的栅电极的端部更远。形成覆盖栅电极和LOCOS氧化物膜的绝缘膜，使得位于栅电极的端部上的端部区域上的绝缘膜的厚度设置成延伸到LOCOS氧化物膜的一部分上从支撑基板的主表面观察，小于在漏极区域之上的源电极的端部下方的绝缘膜的厚度，并且小于栅电极的端部上的绝缘膜的厚度在身体区域之上。

8. 发明申请

US20060255406A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060255406A1
公开(公告)日：2006-11-16
申请号：US11370038
申请日：2006-03-08
申请人： Hisao Ichijo , Hiroyoshi Ogura , Yoshinobu Sato , Teruhisa Ikuta , Toru Terashita
发明人： Hisao Ichijo , Hiroyoshi Ogura , Yoshinobu Sato , Teruhisa Ikuta , Toru Terashita
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76264 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/42364 , H01L29/42368 , H01L29/7824
摘要： An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed adjacently each other, with different types of channel conductivity. The semiconductor device includes a semiconductor substrate, a buried oxide film and a semiconductor layer, and furthermore the semiconductor layer has an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a source region, and a drain region that is positioned in the periphery of the source region, an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a drain region, and a source region is that is positioned in the periphery of the drain region, an isolation trench which isolates the former island-like semiconductor layer from other portions of the semiconductor layer, an isolation trench which isolates the latter island-like semiconductor layer from other portions of the semiconductor layer, and a buffer region, in which the electric potential is fixed to the lowest electric potential in a circuit, which prevents an electrical interference occurred between transistors.
摘要翻译：本发明的目的是提供一种半导体器件，其能够在确保包括多个相互排列的多个MOS晶体管的半导体器件的每个MOS晶体管的漏极和源极之间的击穿电压的同时，减小器件面积，具有不同类型的通道电导率。半导体器件包括半导体衬底，掩埋氧化物膜和半导体层，此外，半导体层具有形成MOS晶体管的岛状半导体层，MOS晶体管具有源极区域和漏极区域位于源极区域周围的岛状半导体层，形成有MOS晶体管的岛状半导体层，MOS晶体管具有漏极区域，源极区域位于漏极区域的周围，将前述岛状半导体层与半导体层的其他部分隔离的隔离沟槽，将后述的岛状半导体层与半导体层的其他部分隔离的隔离沟槽和缓冲区域，其中电位被固定在电路中的最低电位，这防止晶体管之间发生电干扰。

9. 发明申请

US20060118902A1 Lateral semiconductor device and method for producing the same 有权
标题翻译：侧面半导体器件及其制造方法
公开(公告)号：US20060118902A1
公开(公告)日：2006-06-08
申请号：US11242084
申请日：2005-10-04
申请人： Teruhisa Ikuta , Hiroyoshi Ogura , Yoshinobu Sato , Hisao Ichijo
发明人： Teruhisa Ikuta , Hiroyoshi Ogura , Yoshinobu Sato , Hisao Ichijo
IPC分类号： H01L29/76 , H01L23/58 , H01L21/76
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7824 , H01L29/7835
摘要： A high withstand voltage lateral semiconductor device capable of improving its on-state breakdown voltage and safe operation area (SOA) without lowering its current capabilities, and structured so as to be easy to produce. The lateral semiconductor device comprises a second conductivity type second semiconductor region formed in a semiconductor layer so as to be adjacent to or away from a first semiconductor region, a second conductivity type source region, a second conductivity type drain region, and a gate electrode formed on a gate insulating film formed between an end of the source region on the surface of the semiconductor layer and an end of the second semiconductor region, wherein the first semiconductor region is extended from under the source region to partly under the gate electrode, the concentration distribution of a first conductivity type impurity increases in the region ranging from the surface of the semiconductor layer to the embedded insulating film and has a peak under the source region, and the impurity concentration in the semiconductor layer ranging from directly under the first semiconductor region to the embedded insulating film is lower than the surface concentration in the first semiconductor region.
摘要翻译：高耐压横向半导体器件能够在不降低其电流能力的情况下改善其导通电压和安全工作区域（SOA），并且结构化以便于生产。横向半导体器件包括形成在半导体层中以与第一半导体区相邻或离开的第二导电类型的第二半导体区，第二导电类型源极区，第二导电类型漏极区和形成的栅极在形成在所述半导体层的表面上的所述源极区域的端部与所述第二半导体区域的端部之间的栅极绝缘膜上，其中，所述第一半导体区域从所述源极区域的下部延伸到所述栅极电极的下方，在从半导体层的表面到嵌入绝缘膜的范围内的第一导电型杂质的分布增加，并且在源极区域具有峰值，并且半导体层中的杂质浓度范围从第一半导体区域的正下方到嵌入式绝缘膜低于第一绝缘膜中的表面浓度半导体区域。

10. 发明授权

US4925803A Fibrous roll of tubular braid for immobilization of cells and enzymes 失效
标题翻译：用于固定细胞和酶的管状编织物的纤维卷
公开(公告)号：US4925803A
公开(公告)日：1990-05-15
申请号：US107051
申请日：1987-10-13
申请人： Tetsuro Suehiro , Aizo Yamauchi , Hisao Ichijo , Jun'ichi Nagasawa , Noboru Aisaka
发明人： Tetsuro Suehiro , Aizo Yamauchi , Hisao Ichijo , Jun'ichi Nagasawa , Noboru Aisaka
IPC分类号： C12M1/00 , C12M1/40 , C12N11/02 , C12N11/08
CPC分类号： C12N11/08 , C12M25/10
摘要： A fibrous support for immobilizing enzymes and cells is prepared as a roll formed by winding a braid on a tubular frame member. The braid is formed in a tubular shape with a plurality of rovings containing very thin long filaments. The roll is formed by cross-winding of the braid to crush intersecting portions of the tubular braid flat. The roll of braid has an external void ratio of 15 to 30%. The thin long filaments of the tubular braid are obtained by spinning a mixture of polymers to form a plurality of fibers containing a soluble component and an insoluble component, joining the fibers to form a roving, forming a tubular braid from a plurality of the rovings and washing the braid to dissolve out the soluble component to produce separated thin long filaments of the insoluble component.
摘要翻译：制备用于固定酶和细胞的纤维状载体作为通过将编织物卷绕在管状框架构件上而形成的辊。编织物形成为具有多个包含非常细的长丝的粗纱的管状形状。卷筒通过编织物的交叉卷绕而形成，以压缩管状编织物平面的相交部分。辫子卷具有15-30％的外部空隙率。通过纺丝聚合物的混合物以形成多个含有可溶组分和不溶组分的纤维，连接纤维以形成粗纱，从多个粗纱中形成管状编织物，形成管状编织物的细长丝，洗涤编织物以溶解可溶性组分以产生不溶性组分的分离的细长长丝。

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