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1. 发明授权

US07342283B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07342283B2
公开(公告)日：2008-03-11
申请号：US11370038
申请日：2006-03-08
申请人： Hisao Ichijo , Hiroyoshi Ogura , Yoshinobu Sato , Teruhisa Ikuta , Toru Terashita
发明人： Hisao Ichijo , Hiroyoshi Ogura , Yoshinobu Sato , Teruhisa Ikuta , Toru Terashita
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/1203 , H01L21/76264 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/42364 , H01L29/42368 , H01L29/7824
摘要： An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed adjacently each other, with different types of channel conductivity. The semiconductor device includes a semiconductor substrate, a buried oxide film and a semiconductor layer, and furthermore the semiconductor layer has an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a source region, and a drain region that is positioned in the periphery of the source region, an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a drain region, and a source region that is positioned in the periphery of the drain region, an isolation trench which isolates the former island-like semiconductor layer from other portions of the semiconductor layer, an isolation trench which isolates the latter island-like semiconductor layer from other portions of the semiconductor layer, and a buffer region, in which the electric potential is fixed to the lowest electric potential in a circuit, which prevents an electrical interference occurred between transistors.
摘要翻译：本发明的目的是提供一种半导体器件，其能够在确保包括多个相互排列的多个MOS晶体管的半导体器件的每个MOS晶体管的漏极和源极之间的击穿电压的同时，减小器件面积，具有不同类型的通道电导率。半导体器件包括半导体衬底，掩埋氧化物膜和半导体层，此外，半导体层具有形成MOS晶体管的岛状半导体层，MOS晶体管具有源极区域和漏极区域位于源极区域的外围的岛状半导体层，形成有MOS晶体管的岛状半导体层，MOS晶体管具有漏极区域和位于漏极区域的周围的源极区域，将前述岛状半导体层与半导体层的其他部分隔离的隔离沟槽，将后述的岛状半导体层与半导体层的其他部分隔离的隔离沟槽和电位为固定在电路中的最低电位，这防止晶体管之间发生电干扰。

2. 发明申请

US20060255406A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060255406A1
公开(公告)日：2006-11-16
申请号：US11370038
申请日：2006-03-08
申请人： Hisao Ichijo , Hiroyoshi Ogura , Yoshinobu Sato , Teruhisa Ikuta , Toru Terashita
发明人： Hisao Ichijo , Hiroyoshi Ogura , Yoshinobu Sato , Teruhisa Ikuta , Toru Terashita
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76264 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/42364 , H01L29/42368 , H01L29/7824
摘要： An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed adjacently each other, with different types of channel conductivity. The semiconductor device includes a semiconductor substrate, a buried oxide film and a semiconductor layer, and furthermore the semiconductor layer has an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a source region, and a drain region that is positioned in the periphery of the source region, an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a drain region, and a source region is that is positioned in the periphery of the drain region, an isolation trench which isolates the former island-like semiconductor layer from other portions of the semiconductor layer, an isolation trench which isolates the latter island-like semiconductor layer from other portions of the semiconductor layer, and a buffer region, in which the electric potential is fixed to the lowest electric potential in a circuit, which prevents an electrical interference occurred between transistors.
摘要翻译：本发明的目的是提供一种半导体器件，其能够在确保包括多个相互排列的多个MOS晶体管的半导体器件的每个MOS晶体管的漏极和源极之间的击穿电压的同时，减小器件面积，具有不同类型的通道电导率。半导体器件包括半导体衬底，掩埋氧化物膜和半导体层，此外，半导体层具有形成MOS晶体管的岛状半导体层，MOS晶体管具有源极区域和漏极区域位于源极区域周围的岛状半导体层，形成有MOS晶体管的岛状半导体层，MOS晶体管具有漏极区域，源极区域位于漏极区域的周围，将前述岛状半导体层与半导体层的其他部分隔离的隔离沟槽，将后述的岛状半导体层与半导体层的其他部分隔离的隔离沟槽和缓冲区域，其中电位被固定在电路中的最低电位，这防止晶体管之间发生电干扰。

3. 发明申请

US20060118902A1 Lateral semiconductor device and method for producing the same 有权
标题翻译：侧面半导体器件及其制造方法
公开(公告)号：US20060118902A1
公开(公告)日：2006-06-08
申请号：US11242084
申请日：2005-10-04
申请人： Teruhisa Ikuta , Hiroyoshi Ogura , Yoshinobu Sato , Hisao Ichijo
发明人： Teruhisa Ikuta , Hiroyoshi Ogura , Yoshinobu Sato , Hisao Ichijo
IPC分类号： H01L29/76 , H01L23/58 , H01L21/76
CPC分类号： H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7824 , H01L29/7835
摘要： A high withstand voltage lateral semiconductor device capable of improving its on-state breakdown voltage and safe operation area (SOA) without lowering its current capabilities, and structured so as to be easy to produce. The lateral semiconductor device comprises a second conductivity type second semiconductor region formed in a semiconductor layer so as to be adjacent to or away from a first semiconductor region, a second conductivity type source region, a second conductivity type drain region, and a gate electrode formed on a gate insulating film formed between an end of the source region on the surface of the semiconductor layer and an end of the second semiconductor region, wherein the first semiconductor region is extended from under the source region to partly under the gate electrode, the concentration distribution of a first conductivity type impurity increases in the region ranging from the surface of the semiconductor layer to the embedded insulating film and has a peak under the source region, and the impurity concentration in the semiconductor layer ranging from directly under the first semiconductor region to the embedded insulating film is lower than the surface concentration in the first semiconductor region.
摘要翻译：高耐压横向半导体器件能够在不降低其电流能力的情况下改善其导通电压和安全工作区域（SOA），并且结构化以便于生产。横向半导体器件包括形成在半导体层中以与第一半导体区相邻或离开的第二导电类型的第二半导体区，第二导电类型源极区，第二导电类型漏极区和形成的栅极在形成在所述半导体层的表面上的所述源极区域的端部与所述第二半导体区域的端部之间的栅极绝缘膜上，其中，所述第一半导体区域从所述源极区域的下部延伸到所述栅极电极的下方，在从半导体层的表面到嵌入绝缘膜的范围内的第一导电型杂质的分布增加，并且在源极区域具有峰值，并且半导体层中的杂质浓度范围从第一半导体区域的正下方到嵌入式绝缘膜低于第一绝缘膜中的表面浓度半导体区域。

4. 发明授权

US07157772B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07157772B2
公开(公告)日：2007-01-02
申请号：US11167429
申请日：2005-06-28
申请人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
发明人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/7824 , H01L29/402 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/66681
摘要： A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide film is formed such that the thickness of the insulating film at an end-portion region, which is on an end portion of the gate electrode provided to extend over a part of the LOCOS oxide film, as viewed from a main surface of a supporting substrate, is smaller than the thickness of the insulating film below an end portion of the source electrode above the drain region and smaller than the thickness of the insulating film on an end portion of the gate electrode above a body region.
摘要翻译：栅电极的一端延伸到LOCOS氧化膜的一部分上，并且源极电极的一端延伸得比LOCOS氧化膜的一部分上的栅电极的端部更远。形成覆盖栅电极和LOCOS氧化物膜的绝缘膜，使得位于栅电极的端部上的端部区域上的绝缘膜的厚度设置成延伸到LOCOS氧化物膜的一部分上从支撑基板的主表面观察，小于在漏极区域之上的源电极的端部下方的绝缘膜的厚度，并且小于栅电极的端部上的绝缘膜的厚度在身体区域之上。

5. 发明申请

US20060017105A1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060017105A1
公开(公告)日：2006-01-26
申请号：US11167429
申请日：2005-06-28
申请人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
发明人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7824 , H01L29/402 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/66681
摘要： A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide film is formed such that the thickness of the insulating film at an end-portion region, which is on an end portion of the gate electrode provided to extend over a part of the LOCOS oxide film, as viewed from a main surface of a supporting substrate, is smaller than the thickness of the insulating film below an end portion of the source electrode above the drain region and smaller than the thickness of the insulating film on an end portion of the gate electrode above a body region.
摘要翻译：栅电极的一端延伸到LOCOS氧化膜的一部分上，并且源极电极的一端延伸得比LOCOS氧化膜的一部分上的栅电极的端部更远。形成覆盖栅电极和LOCOS氧化物膜的绝缘膜，使得位于栅电极的端部上的端部区域上的绝缘膜的厚度设置成延伸到LOCOS氧化物膜的一部分上从支撑基板的主表面观察，小于在漏极区域之上的源电极的端部下方的绝缘膜的厚度，并且小于栅电极的端部上的绝缘膜的厚度在身体区域之上。

6. 发明授权

US07485972B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07485972B2
公开(公告)日：2009-02-03
申请号：US11356144
申请日：2006-02-17
申请人： Teruhisa Ikuta , Hiroyoshi Ogura , Yoshinobu Sato , Toru Terashita , Hisao Ichijo
发明人： Teruhisa Ikuta , Hiroyoshi Ogura , Yoshinobu Sato , Toru Terashita , Hisao Ichijo
IPC分类号： H01L23/12
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05552 , H01L2224/05624 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/05042 , H01L2924/12036 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Provided is a semiconductor device which includes a conductive bonding pad formed on a semiconductor substrate of the first conduction type via an insulating film and a diffusion layer of the second conduction type formed on a surface of the semiconductor substrate under the bonding pad. Characteristics do not deteriorate even when a breakdown occurs during wire bonding.
摘要翻译：提供了一种半导体器件，其包括形成在第一导电类型的半导体衬底上的导电焊盘，其经由绝缘膜和在接合焊盘下形成在半导体衬底的表面上的第二导电类型的扩散层。即使在引线接合期间发生击穿，特性也不会劣化。

7. 发明申请

US20060202240A1 Semiconductor device 有权
公开(公告)号：US20060202240A1
公开(公告)日：2006-09-14
申请号：US11356144
申请日：2006-02-17
申请人： Teruhisa Ikuta , Hiroyoshi Ogura , Yoshinobu Sato , Toru Terashita , Hisao Ichijo
发明人： Teruhisa Ikuta , Hiroyoshi Ogura , Yoshinobu Sato , Toru Terashita , Hisao Ichijo
IPC分类号： H01L29/76
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05552 , H01L2224/05624 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/05042 , H01L2924/12036 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Provided is a semiconductor device which includes a conductive bonding pad formed on a semiconductor substrate of the first conduction type via an insulating film and a diffusion layer of the second conduction type formed on a surface of the semiconductor substrate under the bonding pad. Characteristics do not deteriorate even when a breakdown occurs during wire bonding.

8. 发明申请

US20060001122A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060001122A1
公开(公告)日：2006-01-05
申请号：US11159134
申请日：2005-06-23
申请人： Hisao Ichijo , Hiroyoshi Ogura , Yoshinobu Sato , Teruhisa Ikuta
发明人： Hisao Ichijo , Hiroyoshi Ogura , Yoshinobu Sato , Teruhisa Ikuta
IPC分类号： H01L23/58
CPC分类号： H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835 , H01L29/78624
摘要： An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate 1; a semiconductor layer 3 having a P− type active region 3a that is formed on the supporting substrate 1, interposing a buried oxide film 2 between the semiconductor layer 3 and the supporting substrate 1; and a gate electrode 16a that is formed on the semiconductor layer 103, interposing a gate oxide film 17 and a part of a LOCOS film 5a between the gate electrode 16a and the semiconductor layer 103, wherein the P− type active region 3a has: an N+ type source region 11; a P type body region 12; a P+ type back gate contact region 14; an N type drain offset region 19; an N+ type drain contact region 20; and an N type drain buffer region 18 that is formed in a limited region between the N type drain offset region 19 and the P type body region 12, and the N type drain buffer region 18 is in contact with a source side end of the LOCOS film 5a and is shallower than the N type drain offset region 19.
摘要翻译：本发明的目的是提供一种能够实现低导通电阻，保持高的漏极 - 源极击穿电压的半导体器件及其制造方法，本发明包括：支撑衬底1; 具有形成在支撑基板1上的P型 - 有源区域3a的半导体层3，在半导体层3和支撑基板1之间插入掩埋氧化膜2; 以及形成在半导体层103上的栅电极16a，在栅电极16a和半导体层103之间插入栅氧化膜17和LOCOS膜5a的一部分，其中P < / SUP>型有源区域3a具有：N + +型源极区域11; P型体区域12; P +型背栅接触区域14; N型漏极偏移区域19; N +型漏极接触区域20; 以及N型漏极缓冲区域18，其形成在N型漏极偏移区域19和P型体区域12之间的有限区域中，并且N型漏极缓冲区域18与LOCOS的源极侧端部接触膜5a并且比N型漏极偏移区域19浅。

9. 发明授权

US07973361B2 High breakdown voltage semiconductor device and fabrication method of the same 有权
标题翻译：高击穿电压半导体器件及其制造方法
公开(公告)号：US07973361B2
公开(公告)日：2011-07-05
申请号：US11362116
申请日：2006-02-27
申请人： Yoshinobu Sato , Hiroyoshi Ogura , Hisao Ichijo , Teruhisa Ikuta , Toru Terashita
发明人： Yoshinobu Sato , Hiroyoshi Ogura , Hisao Ichijo , Teruhisa Ikuta , Toru Terashita
IPC分类号： H01L31/113
CPC分类号： H01L29/0878 , H01L27/1203 , H01L29/063 , H01L29/0847 , H01L29/0886 , H01L29/1083 , H01L29/42364 , H01L29/66659 , H01L29/66681 , H01L29/66772 , H01L29/7824 , H01L29/7835 , H01L29/78621 , H01L29/78654
摘要： A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed on the well region, a P-type drain region formed on the drain offset region, a gate insulating film formed in at least a region interposed between the source region and the drain offset region of the active layer, and a gate electrode formed on the gate insulating film. The device further comprises an N-type deep well region formed under the drain offset region. A concentration peak of N-type impurity for formation of the deep well region is located deeper than a concentration peak of P-type impurity for formation of the drain offset region.
摘要翻译：使用包括支撑衬底，绝缘膜和有源层的SOI衬底形成高耐压电压半导体器件。高击穿电压半导体器件包括在有源层上形成的N型阱区和P型漏极偏移区，形成在阱区上的P型源极区，形成在漏极偏置上的P型漏极区形成在至少位于有源层的源极区域和漏极偏移区域之间的区域中的栅极绝缘膜以及形成在栅极绝缘膜上的栅电极。该器件还包括形成在漏极偏移区域下面的N型深阱区域。用于形成深阱区域的N型杂质的浓度峰位于比用于形成漏极偏移区域的P型杂质的浓度峰值更深的位置。

10. 发明授权

US07408234B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07408234B2
公开(公告)日：2008-08-05
申请号：US11159134
申请日：2005-06-23
申请人： Hisao Ichijo , Hiroyoshi Ogura , Yoshinobu Sato , Teruhisa Ikuta
发明人： Hisao Ichijo , Hiroyoshi Ogura , Yoshinobu Sato , Teruhisa Ikuta
IPC分类号： H01L31/113
CPC分类号： H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835 , H01L29/78624
摘要： An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate; a semiconductor layer having a P− type active region that is formed on the supporting substrate, interposing a buried oxide film between the semiconductor layer and the supporting substrate; and a gate electrode that is formed on the semiconductor layer, interposing a gate oxide film and a part of a LOCOS film between the gate electrode and the semiconductor layer, wherein the P− type active region has: an N+ type source region; a P type body region; a P+ type back gate contact region; an N type drain offset region; an N+ type drain contact region; and an N type drain buffer region that is formed in a limited region between the N type drain offset region and the P type body region, and the N type drain buffer region is in contact with a source side end of the LOCOS film and is shallower than the N type drain offset region.
摘要翻译：本发明的目的是提供一种能够实现低导通电阻并保持高的漏极 - 源极击穿电压的半导体器件及其制造方法，本发明包括：支撑衬底; 形成在所述支撑基板上的具有P-SUP型有源区的半导体层，在所述半导体层和所述支撑基板之间插入掩埋氧化膜; 以及形成在所述半导体层上的栅电极，在所述栅电极和所述半导体层之间插入栅极氧化膜和LOCOS膜的一部分，其中所述P +型有源区具有：类型源区域; P型体区; 一个P + +型背栅接触区; N型漏极偏移区域; 一个N + +型漏极接触区域; 以及形成在N型漏极偏移区域和P型体区域之间的有限区域中的N型漏极缓冲区域，并且N型漏极缓冲区域与LOCOS膜的源极侧端部接触并且较浅比N型漏极偏移区域。

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