专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090195281A1 Timing Signal Generating Circuit, Semiconductor Integrated Circuit Device and Semiconductor Integrated Circuit System to which the Timing Signal Generating Circuit is Applied, and Signal Transmission System 有权
标题翻译：定时信号发生电路，应用了定时信号发生电路的半导体集成电路装置和半导体集成电路系统以及信号传输系统
公开(公告)号：US20090195281A1
公开(公告)日：2009-08-06
申请号：US12358861
申请日：2009-01-23
申请人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
发明人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
IPC分类号： H03L7/00
CPC分类号： H04L7/0337 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03K2005/00052 , H04L7/0025
摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
摘要翻译：半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

2. 发明授权

US08065553B2 Phase interpolator for a timing signal generating circuit 有权
标题翻译：用于定时信号发生电路的相位内插器
公开(公告)号：US08065553B2
公开(公告)日：2011-11-22
申请号：US12358861
申请日：2009-01-23
申请人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
发明人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
IPC分类号： G06F1/04 , G06F1/12 , G06F1/24 , H03J7/04
CPC分类号： H04L7/0337 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03K2005/00052 , H04L7/0025
摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
摘要翻译：半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

3. 发明授权

US07496781B2 Timing signal generating circuit with a master circuit and slave circuits 有权
标题翻译：具有主电路和从电路的定时信号发生电路
公开(公告)号：US07496781B2
公开(公告)日：2009-02-24
申请号：US10278800
申请日：2002-10-24
申请人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
发明人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
IPC分类号： G06F1/04 , G05F1/12 , H03L7/06
CPC分类号： H04L7/0337 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03K2005/00052 , H04L7/0025
摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
摘要翻译：半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

4. 发明申请

US20070063751A1 Clock distribution circuit 有权
标题翻译：时钟分配电路
公开(公告)号：US20070063751A1
公开(公告)日：2007-03-22
申请号：US11392632
申请日：2006-03-30
申请人： Kouichi Kanda , Hirotaka Tamura , Hisakatsu Yamaguchi , Junji Ogawa
发明人： Kouichi Kanda , Hirotaka Tamura , Hisakatsu Yamaguchi , Junji Ogawa
IPC分类号： H03K3/017
CPC分类号： G06F1/10 , H03K5/02
摘要： A clock distribution circuit for suitably generating, transmitting, and receiving clock signals used in circuits that are configured with the same circuit topology is provided. The clock distribution circuit has a transmission buffer circuit that transmits a clock signal and an amplitude amplification buffer circuit that amplifies the amplitude of cross-coupling connections inserted in parallel with the transmission buffer circuit on a transmission path for the clock signal. Wherein the number of transistors having the same conductivity type as the transistors of a differing conductivity type of the transmission buffer circuit and that of the transistors of a differing conductivity type of the amplitude amplification buffer circuit are the same. At least one transistor is provided as a bias adjustment transistor for adjusting bias in each of the transmission buffer circuit and the amplitude amplification buffer circuit, respectively, and bias adjustments are made simultaneously.
摘要翻译：提供了用于适当地生成，发送和接收在具有相同电路拓扑结构的电路中使用的时钟信号的时钟分配电路。时钟分配电路具有发送时钟信号的发送缓冲电路和放大与时钟信号的发送路径上与发送缓冲电路并行插入的交叉耦合连接的振幅的幅度放大缓冲电路。其中具有与透射缓冲电路的不同导电类型的晶体管相同的导电类型的晶体管的数量和不同导电类型的幅度放大缓冲电路的晶体管的数量相同。提供至少一个晶体管作为偏置调整晶体管，用于分别调整每个发送缓冲电路和幅度放大缓冲电路中的偏置，同时进行偏置调整。

5. 发明申请

US20070064781A1 Timing adjustment for data transmitting/receiving circuit 有权
标题翻译：数据发送/接收电路的定时调整
公开(公告)号：US20070064781A1
公开(公告)日：2007-03-22
申请号：US11362174
申请日：2006-02-27
申请人： Hisakatsu Yamaguchi , Kouichi Kanda , Junji Ogawa , Hirotaka Tamura
发明人： Hisakatsu Yamaguchi , Kouichi Kanda , Junji Ogawa , Hirotaka Tamura
IPC分类号： H04L5/16 , H03D3/24
CPC分类号： H04J3/0685 , G06F1/10 , H03L7/00 , H03M9/00 , H04J3/047
摘要： In order to provide a timing adjustment circuit capable of transmitting/receiving data without being affected by process unevenness and power voltage/temperature fluctuations even at a high data transfer rate, the phase of data outputted by a data transmitting unit is compared with the phase of a clock for regulating a data receiving timing of a data receiving unit, and the phase of a clock for regulating a data transmitting timing of the data transmitting unit is adjusted according to the comparison result.
摘要翻译：为了提供即使在高数据传输速率下也能够不受处理不均匀性和电源电压/温度波动的影响而发送/接收数据的定时调整电路，将由数据发送单元输出的数据的相位与根据比较结果调整用于调节数据接收单元的数据接收定时的时钟和用于调节数据发送单元的数据发送定时的时钟的相位。

6. 发明授权

US07786785B2 Peaking control circuit 有权
标题翻译：峰值控制电路
公开(公告)号：US07786785B2
公开(公告)日：2010-08-31
申请号：US12239542
申请日：2008-09-26
申请人： Kouichi Kanda , Hirotaka Tamura , Hisakatsu Yamaguchi , Junji Ogawa
发明人： Kouichi Kanda , Hirotaka Tamura , Hisakatsu Yamaguchi , Junji Ogawa
IPC分类号： G06F1/04
CPC分类号： H03K5/12 , H03F1/42 , H03F3/45183 , H03F3/45632 , H03F2200/36 , H03F2200/435 , H03F2200/447 , H03F2203/45631 , H03F2203/45638 , H03F2203/45681 , H03F2203/45686 , H03H11/1213 , H03H11/1291 , H04L25/028 , H04L25/0288
摘要： There are provided a peaking detection part detecting a peaking amount in an output part of an inductor peaking circuit and a control signal generation part varying a circuit parameter of the inductor peaking circuit based on the peaking amount detected by the peaking detection part. Particularly, the inductor peaking circuit has inductors and resistors inserted in series between the output part and a power supply, and capacitances coupled in parallel between the output part and an earth (GND), and depending on respective values of these inductors, resistors and capacitances, it is possible to suppress a peaking generated in the output part.
摘要翻译：提供了一种检测电感器峰值电路的输出部分中的峰值量的峰值检测部分和基于由峰值检测部分检测到的峰化量来改变电感器峰值电路的电路参数的控制信号产生部分。特别地，电感器峰值电路具有串联插入在输出部分和电源之间的电感器和电阻器，以及在输出部分和地（GND）之间并联耦合的电容，并且取决于这些电感器，电阻器和电容的相应值，可以抑制在输出部分中产生的峰值。

7. 发明申请

US20070063779A1 Clock signal generating and distributing apparatus 有权
标题翻译：时钟信号发生和分配装置
公开(公告)号：US20070063779A1
公开(公告)日：2007-03-22
申请号：US11386789
申请日：2006-03-23
申请人： Kouichi Kanda , Hirotaka Tamura , Hisakatsu Yamaguchi , Junji Ogawa
发明人： Kouichi Kanda , Hirotaka Tamura , Hisakatsu Yamaguchi , Junji Ogawa
IPC分类号： H03B5/08 , H03B5/18
CPC分类号： H03L7/099 , G06F1/04 , G06F1/10 , H03L7/0805 , H03L7/24
摘要： LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.
摘要翻译：采用LC谐振电压控制振荡器作为电压控制振荡器，用于提供即使在几千赫兹或更高的高频区域也能生成和分配高精度的时钟信号的时钟发生和分配装置，并且提供一种分布式VCO型时钟发生和分配装置，其中电压控制振荡器以相同相位振荡，并且其可以产生期望频率的时钟信号，并且即使在达到20GHz的高频区域。此外，连接振荡器的振荡节点的线的电感器部件相对较小，或者LC谐振振荡器通过使用注入锁定而同步地振荡，由此LC谐振电压控制振荡器以相同的相位稳定地振荡。

8. 发明授权

US07863948B2 Clock frequency dividing circuit 有权
标题翻译：时钟分频电路
公开(公告)号：US07863948B2
公开(公告)日：2011-01-04
申请号：US12199168
申请日：2008-08-27
申请人： Hisakatsu Yamaguchi , Kouichi Kanda , Junji Ogawa , Hirotaka Tamura
发明人： Hisakatsu Yamaguchi , Kouichi Kanda , Junji Ogawa , Hirotaka Tamura
IPC分类号： H03B19/00
CPC分类号： H03K27/00 , H03B5/1203 , H03B5/1228 , H03B5/1243 , H03B19/00
摘要： A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each of the frequency dividing circuits includes a mixer, an adding circuit, and a phase circuit. The first frequency dividing circuit and the second frequency dividing circuit are coupled in loop shape via a first coupling circuit and a second coupling circuit. The first coupling circuit receives a first output signal of the first frequency dividing circuit to output a second external input signal to the second frequency dividing circuit, and the second coupling circuit receives a second output signal of the second frequency dividing circuit to output a first external input signal to the first frequency dividing circuit, and a clock frequency dividing circuit with a high loop gain and a wide lock range can be realized.
摘要翻译：提供第一分频电路和第二分频电路，这些电路对从外部部分注入的两相外部时钟进行分频，以输出具有相位保证的四相时钟。每个分频电路包括混频器，加法电路和相电路。第一分频电路和第二分频电路经由第一耦合电路和第二耦合电路以环形形式耦合。第一耦合电路接收第一分频电路的第一输出信号，以将第二外部输入信号输出到第二分频电路，第二耦合电路接收第二分频电路的第二输出信号，以输出第一外部输入信号到第一分频电路，并且可以实现具有高环路增益和宽锁定范围的时钟分频电路。

9. 发明授权

US07863987B2 Clock signal generating and distributing apparatus 有权
标题翻译：时钟信号发生和分配装置
公开(公告)号：US07863987B2
公开(公告)日：2011-01-04
申请号：US11386789
申请日：2006-03-23
申请人： Kouichi Kanda , Hirotaka Tamura , Hisakatsu Yamaguchi , Junji Ogawa
发明人： Kouichi Kanda , Hirotaka Tamura , Hisakatsu Yamaguchi , Junji Ogawa
IPC分类号： H03B5/18 , H03B9/14
CPC分类号： H03L7/099 , G06F1/04 , G06F1/10 , H03L7/0805 , H03L7/24
摘要： LC resonant voltage control oscillators are adopted as voltage control oscillators for the purpose of providing a clock generating and distributing apparatus that can generate and distribute a clock signal of high precision even in a high-frequency region of several giga hertz or higher, and of providing a distributive VCO-type clock generating and distributing apparatus in which voltage control oscillators oscillate in the same phase, and which can generate a clock signal of a desired frequency and distributes a high-frequency clock signal to each part within a chip more stably even in a high-frequency region reaching 20 GHz. Furthermore, an inductor component of a wire connecting the oscillation nodes of the oscillators is made relatively small, or the LC resonant oscillators are oscillated in synchronization by using injection locking, whereby the LC resonant voltage control oscillators stably oscillate in the same phase.
摘要翻译：采用LC谐振电压控制振荡器作为电压控制振荡器，用于提供即使在几千赫兹或更高的高频区域也能生成和分配高精度的时钟信号的时钟发生和分配装置，并且提供一种分布式VCO型时钟发生和分配装置，其中电压控制振荡器以相同相位振荡，并且其可以产生期望频率的时钟信号，并且即使在达到20GHz的高频区域。此外，连接振荡器的振荡节点的线的电感器部件相对较小，或者LC谐振振荡器通过使用注入锁定而同步地振荡，由此LC谐振电压控制振荡器以相同的相位稳定地振荡。

10. 发明授权

US07653169B2 Timing adjustment for data transmitting/receiving circuit 有权
标题翻译：数据发送/接收电路的定时调整
公开(公告)号：US07653169B2
公开(公告)日：2010-01-26
申请号：US11362174
申请日：2006-02-27
申请人： Hisakatsu Yamaguchi , Kouichi Kanda , Junji Ogawa , Hirotaka Tamura
发明人： Hisakatsu Yamaguchi , Kouichi Kanda , Junji Ogawa , Hirotaka Tamura
IPC分类号： H03D3/24
CPC分类号： H04J3/0685 , G06F1/10 , H03L7/00 , H03M9/00 , H04J3/047
摘要： In order to provide a timing adjustment circuit capable of transmitting/receiving data without being affected by process unevenness and power voltage/temperature fluctuations even at a high data transfer rate, the phase of data outputted by a data transmitting unit is compared with the phase of a clock for regulating a data receiving timing of a data receiving unit, and the phase of a clock for regulating a data transmitting timing of the data transmitting unit is adjusted according to the comparison result.
摘要翻译：为了提供即使在高数据传输速率下也能够不受处理不均匀性和电源电压/温度波动的影响而发送/接收数据的定时调整电路，将由数据发送单元输出的数据的相位与根据比较结果调整用于调节数据接收单元的数据接收定时的时钟和用于调节数据发送单元的数据发送定时的时钟的相位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式