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1. 发明授权

US07026679B2 Semiconductor integrated circuit device and the process of manufacturing the same having poly-silicon plug, wiring trenches and bit lines formed in the wiring trenches having a width finer than a predetermined size 有权
标题翻译：半导体集成电路器件及其制造方法，其具有形成在布线沟槽中的具有比预定尺寸更窄的宽度的多晶硅插塞，布线沟槽和位线
公开(公告)号：US07026679B2
公开(公告)日：2006-04-11
申请号：US10755393
申请日：2004-01-13
申请人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
发明人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/115 , H01L27/11526
摘要： A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
摘要翻译：通过使位线的宽度比由光刻的分辨率的极限决定的最小尺寸更窄，DRAM的存储单元的尺寸减小。通过在形成于氧化硅膜中的布线沟槽的内壁上形成氧化硅膜，并且在氧化硅膜内部形成位线，使位线变细。沉积形成在沟槽中的氧化硅膜，使得氧化硅膜具有比布线沟槽的宽度的一半更薄的厚度，并且在氧化硅膜内部的微细间隙中埋入金属膜作为位的材料线。

2. 发明授权

US06762449B2 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND THE PROCESS OF MANUFACTURING THE SAME HAVING POLY-SILICON PLUG, WIRING TRENCHES AND BIT LINES FORMED IN THE WIRING TRENCHES HAVING A WIDTH FINER THAN A PREDETERMINED SIZE 有权
标题翻译：半导体集成电路器件及其制造方法，其制造方法具有在具有超过预定尺寸的宽度的布线中形成的多硅插头，布线和布线
公开(公告)号：US06762449B2
公开(公告)日：2004-07-13
申请号：US09548966
申请日：2000-04-13
申请人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
发明人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
IPC分类号： H01L27108
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/115 , H01L27/11526
摘要： A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
摘要翻译：通过使位线的宽度比由光刻的分辨率的极限决定的最小尺寸更窄，DRAM的存储单元的尺寸减小。通过在形成于氧化硅膜中的布线沟槽的内壁上形成氧化硅膜，并且在氧化硅膜内部形成位线，使位线变细。沉积形成在沟槽中的氧化硅膜，使得氧化硅膜具有比布线沟槽的宽度的一半更薄的厚度，并且在氧化硅膜内部的微细间隙中埋入金属膜作为位的材料线。

3. 发明授权

US06867092B2 Semiconductor integrated circuit device and the process of manufacturing the same for reducing the size of a memory cell by making the width of a bit line than a predetermined minimum size 有权
标题翻译：半导体集成电路器件及其制造方法，用于通过使位线的宽度大于预定的最小尺寸来减小存储器单元的尺寸
公开(公告)号：US06867092B2
公开(公告)日：2005-03-15
申请号：US10013475
申请日：2001-12-13
申请人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
发明人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
IPC分类号： H01L21/768 , H01L21/8242 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/76 , H01L21/20
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/115 , H01L27/11526
摘要： A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
摘要翻译：通过使位线的宽度比由光刻的分辨率的极限决定的最小尺寸更窄，DRAM的存储单元的尺寸减小。通过在形成于氧化硅膜中的布线沟槽的内壁上形成氧化硅膜，并且在氧化硅膜内部形成位线，使位线变细。沉积形成在沟槽中的氧化硅膜，使得氧化硅膜具有比布线沟槽的宽度的一半更薄的厚度，并且在氧化硅膜内部的微细间隙中埋入金属膜作为位的材料线。

4. 发明授权

US06287914B1 Method of forming a MISFET device with a bit line completely surrounded by dielectric 有权
标题翻译：用绝缘体完全包围的位线形成MISFET器件的方法
公开(公告)号：US06287914B1
公开(公告)日：2001-09-11
申请号：US09640013
申请日：2000-08-17
申请人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
发明人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
IPC分类号： H01L218242
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/115 , H01L27/11526
摘要： A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
摘要翻译：通过使位线的宽度比由光刻的分辨率的极限决定的最小尺寸更窄，DRAM的存储单元的尺寸减小。通过在形成于氧化硅膜中的布线沟槽的内壁上形成氧化硅膜，并且在氧化硅膜内部形成位线，使位线变细。沉积形成在沟槽中的氧化硅膜，使得氧化硅膜具有比布线沟槽的宽度的一半更薄的厚度，并且在氧化硅膜内部的微细间隙中埋入金属膜作为位的材料线。

5. 发明授权

US08222686B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08222686B2
公开(公告)日：2012-07-17
申请号：US13097731
申请日：2011-04-29
申请人： Shoji Shukuri
发明人： Shoji Shukuri
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/34 , H01L21/28273 , H01L21/28282 , H01L23/535 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/1157 , H01L27/11573 , H01L29/42328 , H01L29/42344 , H01L29/42368 , H01L29/45 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a nonvolatile memory cell which includes a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and being adjacent to the control gate electrode, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, the control gate electrode having a different type conductivity than that of the memory gate electrode. A manufacturing technique for a semiconductor device including a nonvolatile memory cell having control gate and memory gate electrodes is also featured.
摘要翻译：一种具有非易失性存储单元的半导体器件，包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的控制电极，用作控制栅电极的栅极绝缘体的第一绝缘膜，形成在所述半导体衬底上的第二绝缘膜，以及形成在所述第二绝缘膜上并与所述控制栅电极相邻的存储栅电极，所述第二绝缘膜用作所述存储栅电极的栅极绝缘体，并且具有非导电电荷所述控制栅电极具有与所述存储栅电极不同的导电类型。还提出了一种包括具有控制栅极和存储栅电极的非易失性存储单元的半导体器件的制造技术。

6. 发明申请

US20120112265A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120112265A1
公开(公告)日：2012-05-10
申请号：US13350703
申请日：2012-01-13
申请人： Natsuo AJIKA , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo AJIKA , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

7. 发明申请

US20100149875A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100149875A1
公开(公告)日：2010-06-17
申请号：US12714750
申请日：2010-03-01
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及非易失性半导体存储器，更具体地说涉及具有增加的程序吞吐量的非易失性半导体存储器本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

8. 发明申请

US20090090961A1 Non-Volatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090090961A1
公开(公告)日：2009-04-09
申请号：US12246193
申请日：2008-10-06
申请人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

9. 发明授权

US07166893B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07166893B2
公开(公告)日：2007-01-23
申请号：US10252101
申请日：2002-09-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
摘要翻译：能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

10. 发明授权

US07119406B2 Semiconductor integrated circuit device having deposited layer for gate insulation 有权
公开(公告)号：US07119406B2
公开(公告)日：2006-10-10
申请号：US11178375
申请日：2005-07-12
申请人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/62 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.

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