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1. 发明授权

US5131072A Neurocomputer with analog signal bus 失效
标题翻译：具有模拟信号总线的神经元
公开(公告)号：US5131072A
公开(公告)日：1992-07-14
申请号：US474055
申请日：1990-04-30
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Yoshihide Sugiura , Kazuo Asakawa , Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Chikara Tsuchiya , Katsuya Ishikawa , Hiromu Iwamoto
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Yoshihide Sugiura , Kazuo Asakawa , Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Chikara Tsuchiya , Katsuya Ishikawa , Hiromu Iwamoto
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/063 , G06N3/04 , G06N3/0635
摘要： An analogue neuron processor (ANP) performs an operation of sum-of-products of a time divisional analog input signal sequentially input from an analog signal bus and weight data and output an analog signal to an analog signal bus through a nonlinear circuit. A layered type or a feedback type neural network is formed of ANPs. The neural network reads necessary control data from a control pattern memory under the control of micro sequencer and reads the necessary weight data from the weight memory thereby realizing a neuron computer. The neuron computer connects a plurality of ANPs by using a single analog bus, thereby greatly decreasing the number of the wires used for the neural network and also decreasing the size of the circuit. A plurality of ANPs in a single layer simultaneously receives analog signal from an analog bus and carries out a parallel operation in the same time period and ANPs in different layers perform a parallel operation in a pipeline manner, thereby increasing a speed of an operation. Accordingly, the prsent invention can provide a neuron computer with a high practicality.

2. 发明授权

US5220559A Neuron architecture 失效
标题翻译： NEURON建筑
公开(公告)号：US5220559A
公开(公告)日：1993-06-15
申请号：US400826
申请日：1989-08-30
申请人： Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Kazuo Asakawa , Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa , Yoshihide Sugiura
发明人： Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Kazuo Asakawa , Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa , Yoshihide Sugiura
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.

3. 发明授权

US5216746A Error absorbing system in a neuron computer 失效
标题翻译：神经电脑中的错误吸收系统
公开(公告)号：US5216746A
公开(公告)日：1993-06-01
申请号：US486647
申请日：1990-02-28
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors. The weight correcting unit calculates a correct weight using a gain based on the detection output voltage output from the second analog bus. A weight memory stores the weight corrected by the weight correcting unit.

4. 发明授权

US5142666A Learning system in a neuron computer 失效
标题翻译：神经电脑学习系统
公开(公告)号：US5142666A
公开(公告)日：1992-08-25
申请号：US486644
申请日：1990-02-28
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
IPC分类号： G06G7/60 , G06F15/18 , G06N3/02 , G06N3/04 , G06N3/08 , G06N99/00
CPC分类号： G06N3/04
摘要： A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.

5. 发明授权

US08255438B2 Storage control device 有权
标题翻译：存储控制装置
公开(公告)号：US08255438B2
公开(公告)日：2012-08-28
申请号：US12385698
申请日：2009-04-16
申请人： Naoki Yamagata , Toshiharu Matsuda
发明人： Naoki Yamagata , Toshiharu Matsuda
IPC分类号： G06F12/00
CPC分类号： G06F12/0238 , G06F12/0246 , G06F2212/7207
摘要： The storage control device includes: a control unit that stores a data file that includes main data and file information in a write-once type storage medium having a data information area containing a plurality of clusters having a predetermined size; an acquisition unit that acquire size information of the clusters from the storage medium; a calculation unit that calculates a number of clusters required for storing file information corresponding to each data file in data storing area using the number of data files to be stored in the storage medium, the size of file information, and the size information of the clusters; and a setting unit that sets a data information area corresponding to the number of clusters calculated by the calculation unit as a storage area for file information.
摘要翻译：存储控制装置包括：控制单元，其将包含主数据和文件信息的数据文件存储在具有包含具有预定大小的多个簇的数据信息区域的一次写入型存储介质中; 获取单元，其从所述存储介质获取所述簇的大小信息; 计算单元，使用要存储在存储介质中的数据文件的数量，文件信息的大小和簇的大小信息来计算存储与数据存储区域中的每个数据文件相对应的文件信息所需的集群数量 ; 以及设置单元，其将与由计算单元计算的聚类数相对应的数据信息区域设置为文件信息的存储区域。

6. 发明授权

US4873366A Process for producing 2,6-naphthalenedicarboxylic acid 失效
标题翻译： 2,6-萘二甲酸的制备方法
公开(公告)号：US4873366A
公开(公告)日：1989-10-10
申请号：US177774
申请日：1988-04-05
申请人： Toshiharu Matsuda , Atsushi Sasakawa , Shoichiro Hayashi , Yutaka Konai
发明人： Toshiharu Matsuda , Atsushi Sasakawa , Shoichiro Hayashi , Yutaka Konai
IPC分类号： B01J35/04 , B01J27/08 , B01J27/128 , C07B61/00 , C07C51/00 , C07C51/265 , C07C63/38 , C07C67/00
CPC分类号： C07C51/265
摘要： Disclosed in the present invention is a process for producing 2,6-naphthalenedicarboxylic acid comprising oxidizing 2,6-diisopropylnaphthalene or its partially oxidized intermediate with molecular oxygen in a solvent containing at least 50% by weight of an aliphatic monocarboxylic acid, having not more than three carbon atoms, in the presence of a catalyst composed of (i) a heavy metal comprising cobalt and/or manganese and (ii) bromine, and a salt of an inorganic acid having an acid dissociation constant Ka smaller than 1.34.times.10.sup.-5 (at 25.degree. C.) and a vapor pressure lower than that of the aliphatic monocarboxylic acid used as the solvent. According to the process of this invention, 2,6-naphthalenedicarboxylic acid of high bulk density can be obtained in a high yield and with high purity.

7. 发明授权

US4667477A Cryopump and method of operating same 失效
标题翻译：冷冻库和操作方法相同
公开(公告)号：US4667477A
公开(公告)日：1987-05-26
申请号：US716941
申请日：1985-03-28
申请人： Toshiharu Matsuda , Norihide Saho , Minoru Imamura , Nobuyuki Hosomi
发明人： Toshiharu Matsuda , Norihide Saho , Minoru Imamura , Nobuyuki Hosomi
IPC分类号： B01D8/00 , F04B37/08
CPC分类号： F04B37/08 , B01D8/00 , Y10S417/901
摘要： A cryopump and a method of operating the same, with the cryopump being provided with a cryopanel adapted to be cooled with cold heat generated by a cold heat generating device, and remove the ambient gas, and a device for regulating the temperature of said cryopanel in accordance with the ambient conditions. The cryopump is capable of varying its pumping speed by regulating in accordance with the ambient conditions the temperature of the cryopanel which is adapted to be cooled with cold heat and remove the ambient gas.
摘要翻译：一种低温泵及其操作方法，其中低温泵设置有适于由冷热发生装置产生的冷热冷却的冷冻板，并且除去环境气体;以及用于调节所述冷冻板的温度的装置符合环境条件。低温泵能够通过根据环境条件调节适合于冷热冷却的冷冻板的温度并去除环境气体来改变其泵送速度。

8. 发明授权

US4510771A Cryostat with refrigerating machine 失效
标题翻译：冷冻机用冷冻机
公开(公告)号：US4510771A
公开(公告)日：1985-04-16
申请号：US520515
申请日：1983-08-04
申请人： Toshiharu Matsuda , Minoru Imamura , Norihide Saho
发明人： Toshiharu Matsuda , Minoru Imamura , Norihide Saho
IPC分类号： F25B9/00 , F17C3/08 , F25B9/10 , F25B9/14 , F25D13/00 , F25D19/00 , F25B19/00
CPC分类号： F25D19/006 , F17C3/085 , F17C2203/0687 , F17C2270/0536 , F25B9/10 , F25B9/14 , Y10S505/892
摘要： In a cryostat composed of a first liquefied gas reservoir containing therein a first liquefied gas, a second liquefied gas reservoir containing therein a second liquefied gas, which has a boiling point higher than that of the first liquefied gas, the second liquefied gas reservoir being provided around the first liquefied reservoir in order to reduce the heat leak into the first liquefied gas reservoir, and an outer wall surrounding the second liquefied gas reservoir through a vacuum space, a refrigerating machine is arranged in the space within the outer wall and cools the second liquefied gas in the second and first liquefied gas reservoirs and the first liquefied gas whereby the cryostat may be used continuously for a long period of time without periodically supplying the second and third gases.
摘要翻译：在由含有第一液化气体的第一液化气储存器构成的低温恒温器中，含有沸点高于第一液化气体的沸点的第二液化气体的第二液化气储存器，设置有第二液化气储存器为了减少第一液化气储存器的热量泄漏和通过真空空间围绕第二液化气储存器的外壁，在第一液化储存器周围，在外壁内的空间内设置有冷却机构，在第二和第一液化气体储存器中的液化气体和第一液化气体，由此低温恒温器可以连续使用长时间而不周期性地供应第二和第三气体。

9. 发明申请

US20090322905A1 Storage control device 审中-公开
标题翻译：存储控制装置
公开(公告)号：US20090322905A1
公开(公告)日：2009-12-31
申请号：US12385697
申请日：2009-04-16
申请人： Toshiharu Matsuda , Naoki Yamagata
发明人： Toshiharu Matsuda , Naoki Yamagata
IPC分类号： H04N5/76
CPC分类号： G06F3/0604 , H04N5/772 , H04N5/907 , H04N9/804 , H04N21/4184 , H04N21/4223 , H04N21/4334
摘要： A storage control device includes: a memory where a data file is temporarily stored; a read-out unit that sequentially reads out divided data segments of the data file; a storage medium that includes data storage areas having small areas and data management areas each corresponding to the small area, so as to store each of the data segments into small areas and store at least one of first link information and second link information into the data management areas; a first instruction unit that issues an instruction for procuring consecutive data management areas corresponding to a data size of data segments; a second instruction unit that issues an instruction for writing the first link information into the data management areas excluding a trailing-end data management area; and a third instruction unit that issues an instruction for sequentially writing the data segment into the data storage areas.
摘要翻译：存储控制装置包括：临时存储数据文件的存储器; 读出单元，其顺序读出数据文件的分割数据段; 存储介质，其包括具有小区域的数据存储区域和每个对应于小区域的数据管理区域，以将每个数据段存储到小区域中，并将第一链接信息和第二链接信息中的至少一个存储到数据中管理区; 第一指令单元，其发出用于采购与数据段的数据大小对应的连续数据管理区域的指令; 第二指令单元，其发出将第一链接信息写入除了后端数据管理区域之外的数据管理区域的指令; 以及第三指令单元，其发出用于将数据段顺序地写入数据存储区域的指令。

10. 发明授权

US4982583A Air conditioner for railway vehicles 失效
标题翻译：铁路车辆空调
公开(公告)号：US4982583A
公开(公告)日：1991-01-08
申请号：US465891
申请日：1990-01-16
申请人： Toshiharu Matsuda , Yoshinao Okumoto , Nobuyuki Fugiyama , Yoshichika Fukushima
发明人： Toshiharu Matsuda , Yoshinao Okumoto , Nobuyuki Fugiyama , Yoshichika Fukushima
IPC分类号： B60H1/32 , B61D27/00
CPC分类号： B61D27/0018 , B60H1/3204 , Y10S62/16
摘要： A flat air conditioner for railway vehicle for installation on the roof of a vehicle is advantageous from the viewpoint of reducing air resistance to the vehicle and the design of the vehicle. The present invention provides such a vehicular air conditioner incorporating an horizontally longer compressor or compressors disposed with the longitudinal axes in a horizontal plane or disposed in a return air chamber to construct the air conditioner in a flat configuration with a small height and in a compact construction.

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