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1. 发明授权

US5131072A Neurocomputer with analog signal bus 失效
标题翻译：具有模拟信号总线的神经元
公开(公告)号：US5131072A
公开(公告)日：1992-07-14
申请号：US474055
申请日：1990-04-30
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Yoshihide Sugiura , Kazuo Asakawa , Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Chikara Tsuchiya , Katsuya Ishikawa , Hiromu Iwamoto
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Yoshihide Sugiura , Kazuo Asakawa , Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Chikara Tsuchiya , Katsuya Ishikawa , Hiromu Iwamoto
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/063 , G06N3/04 , G06N3/0635
摘要： An analogue neuron processor (ANP) performs an operation of sum-of-products of a time divisional analog input signal sequentially input from an analog signal bus and weight data and output an analog signal to an analog signal bus through a nonlinear circuit. A layered type or a feedback type neural network is formed of ANPs. The neural network reads necessary control data from a control pattern memory under the control of micro sequencer and reads the necessary weight data from the weight memory thereby realizing a neuron computer. The neuron computer connects a plurality of ANPs by using a single analog bus, thereby greatly decreasing the number of the wires used for the neural network and also decreasing the size of the circuit. A plurality of ANPs in a single layer simultaneously receives analog signal from an analog bus and carries out a parallel operation in the same time period and ANPs in different layers perform a parallel operation in a pipeline manner, thereby increasing a speed of an operation. Accordingly, the prsent invention can provide a neuron computer with a high practicality.

2. 发明授权

US5220559A Neuron architecture 失效
标题翻译： NEURON建筑
公开(公告)号：US5220559A
公开(公告)日：1993-06-15
申请号：US400826
申请日：1989-08-30
申请人： Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Kazuo Asakawa , Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa , Yoshihide Sugiura
发明人： Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Kazuo Asakawa , Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa , Yoshihide Sugiura
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.

3. 发明授权

US5216746A Error absorbing system in a neuron computer 失效
标题翻译：神经电脑中的错误吸收系统
公开(公告)号：US5216746A
公开(公告)日：1993-06-01
申请号：US486647
申请日：1990-02-28
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors. The weight correcting unit calculates a correct weight using a gain based on the detection output voltage output from the second analog bus. A weight memory stores the weight corrected by the weight correcting unit.

4. 发明授权

US5142666A Learning system in a neuron computer 失效
标题翻译：神经电脑学习系统
公开(公告)号：US5142666A
公开(公告)日：1992-08-25
申请号：US486644
申请日：1990-02-28
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
IPC分类号： G06G7/60 , G06F15/18 , G06N3/02 , G06N3/04 , G06N3/08 , G06N99/00
CPC分类号： G06N3/04
摘要： A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.

5. 发明授权

US4456840A Comparator circuit 失效
标题翻译：比较器电路
公开(公告)号：US4456840A
公开(公告)日：1984-06-26
申请号：US329947
申请日：1981-12-11
申请人： Tetsuo Ide , Hiromu Iwamoto
发明人： Tetsuo Ide , Hiromu Iwamoto
IPC分类号： G01R19/165 , H03K3/023 , H03K3/0233 , H03K5/08 , H03K5/22
CPC分类号： H03K3/02337 , H03K3/023
摘要： A comparator circuit providing a hysteresis characteristic which does not change a hysteresis width even if a power supply voltage changes is disclosed. The comparator circuit comprises a differential amplifier including an input terminal, a reference terminal and an output terminal; an input voltage terminal to which an input voltage is applied; a reference voltage terminal to which a reference voltage is applied; at least one level shift means connected between said input voltage terminal and said input terminal, or between said reference voltage terminal and said reference terminal; a current source means connected to the output of said level shift means; and control means for controlling the current value of said current source means in accordance with the output level of said output terminal.
摘要翻译：提供即使电源电压变化也不改变滞后宽度的滞后特性的比较器电路。比较器电路包括：差分放大器，包括输入端子，参考端子和输出端子; 施加输入电压的输入电压端子; 施加基准电压的参考电压端子; 连接在所述输入电压端子和所述输入端子之间或所述参考电压端子与所述参考端子之间的至少一个电平移动装置; 连接到所述电平移位装置的输出的电流源装置; 以及控制装置，用于根据所述输出端子的输出电平来控制所述电流源装置的电流值。

6. 发明授权

US4544912A Scale switchable digital-to-analog converter 失效
标题翻译：可切换数模转换器
公开(公告)号：US4544912A
公开(公告)日：1985-10-01
申请号：US574209
申请日：1984-01-27
申请人： Hiromu Iwamoto , Haruo Tamada
发明人： Hiromu Iwamoto , Haruo Tamada
IPC分类号： H03M1/78 , H03M1/00 , H03K13/05
CPC分类号： H03M1/0612
摘要： A D/A converter of the resistor ladder type provided with full-scale switching circuits between the output terminal of the series connected resistors and ground for selecting the value of resistance of the full-scale control resistor, thereby selecting the value of the full-scale voltage.
摘要翻译：电阻梯型的AD / A转换器在串联电阻的输出端和地之间提供满量程开关电路，用于选择满量程控制电阻的电阻值，从而选择满量程的值电压。

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