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    • 2. 发明授权
    • Vertical synchronizing signal detector circuit
    • 垂直同步信号检测电路
    • US4238770A
    • 1980-12-09
    • US79252
    • 1979-09-27
    • Masaharu KobayashiTakao AraiTakashi HoshinoHiroyuki KimuraKeizo Nishimura
    • Masaharu KobayashiTakao AraiTakashi HoshinoHiroyuki KimuraKeizo Nishimura
    • G11B20/10H04N5/10H04N5/932
    • H04N5/932H04N5/10
    • There is disclosed a vertical synchronizing signal detector circuit for use with a PCM recording/reproducing system which records and reproduces audio signals with pulse code modulation by the use of a home VTR system or a part thereof. The vertical synchronizing signal detector circuit comprises an input terminal for receiving a composite synchronizing signal including a horizontal synchronizing signal and a vertical synchronizing signal, an output terminal for providing a vertical synchronizing pulse synchronized with the vertical synchronizing signal, a clock pulse generator circuit connected to the input terminal and adapted to generate a clock pulse having half the period of the horizontal synchronizing signal and a phase lag therefrom of one-fourth the period thereof, a vertical synchronizing signal extractor circuit connected to the input terminal and the clock pulse generator circuit and adapted to compare the vertical synchronizing signal with a reference waveform pattern for the vertical synchronizing signal so as to generate a vertical synchronizing signal output synchronized with the vertical synchronizing signal only when the comparison results in a complete coincidence, and a vertical synchronizing signal compensator circuit connected to the vertical synchronizing signal extractor circuit and the clock pulse generator circuit and responsive to the vertical synchronizing signal output to provide this output at the output terminal and simultaneously store the same temporarily, the vertical synchronizing signal compensator circuit being also adapted to provide the stored vertical synchronizing signal output at the output terminal when the vertical synchronizing signal output is not received, whereby the vertical synchronizing pulse is produced at correct timing even if the vertical synchronizing signal is absent in the composite synchronizing signal because of a dropout or the like.
    • 公开了一种与PCM记录/再现系统一起使用的垂直同步信号检测器电路,其通过使用家用VTR系统或其一部分来记录和再现具有脉冲编码调制的音频信号。 垂直同步信号检测电路包括:输入端子,用于接收包括水平同步信号和垂直同步信号的复合同步信号;输出端,用于提供与垂直同步信号同步的垂直同步脉冲;时钟脉冲发生器电路,连接到 所述输入端子适于产生具有所述水平同步信号的一半周期的时钟脉冲及其四分之一周期的相位滞后;垂直同步信号提取器电路,连接到所述输入端子和所述时钟脉冲发生器电路;以及 适于将垂直同步信号与用于垂直同步信号的参考波形图案进行比较,以便仅当比较导致完全符合时产生与垂直同步信号同步的垂直同步信号,并且垂直同步信号 l补偿电路连接到垂直同步信号提取器电路和时钟脉冲发生器电路,并且响应于垂直同步信号输出以在输出端提供该输出并同时暂时存储,垂直同步信号补偿器电路还适于 当没有接收到垂直同步信号输出时,在输出端提供所存储的垂直同步信号,由此,即使在复合同步信号中缺少垂直同步信号,因此在正确定时产生垂直同步脉冲, 喜欢。
    • 3. 发明授权
    • Circuit for reproducing and demodulating modulated digital signals
    • 用于再现和解调调制数字信号的电路
    • US4472686A
    • 1984-09-18
    • US311023
    • 1981-10-13
    • Keizo NishimuraHiroyuki KimuraYasunori Kanazawa
    • Keizo NishimuraHiroyuki KimuraYasunori Kanazawa
    • H04L7/00H04L7/02H04L7/04H04L25/48H04L25/49H03K7/10
    • H04L25/4904H04L7/0066H04L7/042
    • A circuit for reproducing and demodulating a modulated digital signal which is modulated in a predetermined modulation system such as MFM, EFM and so on. A phase of a clock having a frequency multiplied by an integral number of a bit frequency of the modulated digital signal, is restricted or controlled by a signal showing that a predetermined pattern of the modulated digital signal occurred. The modulated digital signal is demodulated by the thus restricted clock to produce digital informations "0" and "1". A main requirement for detecting the predetermined pattern of the modulated digital signal, is that a reproduced modulated digital signal is reliable. In order to compensate for the drop-out of the modulated digital signal, the demodulation circuit is provided with a modulated digital signal reproducing circuit for complementing a predetermined signal pattern when the drop-out occurred.
    • 用于再现和解调在诸如MFM,EFM等的预定调制系统中调制的调制数字信号的电路。 具有乘以调制数字信号的位频的整数的频率的时钟的相位受到表示调制数字信号的预定模式发生的信号的限制或控制。 经调制的数字信号被这样受限的时钟解调,产生数字信息“0”和“1”。 检测调制数字信号的预定模式的主要要求是再现的调制数字信号是可靠的。 为了补偿调制的数字信号的丢失,解调电路设置有调制的数字信号再现电路,用于当出现发生时补充预定的信号模式。