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    • 1. 发明授权
    • Vertical synchronizing signal detector circuit
    • 垂直同步信号检测电路
    • US4238770A
    • 1980-12-09
    • US79252
    • 1979-09-27
    • Masaharu KobayashiTakao AraiTakashi HoshinoHiroyuki KimuraKeizo Nishimura
    • Masaharu KobayashiTakao AraiTakashi HoshinoHiroyuki KimuraKeizo Nishimura
    • G11B20/10H04N5/10H04N5/932
    • H04N5/932H04N5/10
    • There is disclosed a vertical synchronizing signal detector circuit for use with a PCM recording/reproducing system which records and reproduces audio signals with pulse code modulation by the use of a home VTR system or a part thereof. The vertical synchronizing signal detector circuit comprises an input terminal for receiving a composite synchronizing signal including a horizontal synchronizing signal and a vertical synchronizing signal, an output terminal for providing a vertical synchronizing pulse synchronized with the vertical synchronizing signal, a clock pulse generator circuit connected to the input terminal and adapted to generate a clock pulse having half the period of the horizontal synchronizing signal and a phase lag therefrom of one-fourth the period thereof, a vertical synchronizing signal extractor circuit connected to the input terminal and the clock pulse generator circuit and adapted to compare the vertical synchronizing signal with a reference waveform pattern for the vertical synchronizing signal so as to generate a vertical synchronizing signal output synchronized with the vertical synchronizing signal only when the comparison results in a complete coincidence, and a vertical synchronizing signal compensator circuit connected to the vertical synchronizing signal extractor circuit and the clock pulse generator circuit and responsive to the vertical synchronizing signal output to provide this output at the output terminal and simultaneously store the same temporarily, the vertical synchronizing signal compensator circuit being also adapted to provide the stored vertical synchronizing signal output at the output terminal when the vertical synchronizing signal output is not received, whereby the vertical synchronizing pulse is produced at correct timing even if the vertical synchronizing signal is absent in the composite synchronizing signal because of a dropout or the like.
    • 公开了一种与PCM记录/再现系统一起使用的垂直同步信号检测器电路,其通过使用家用VTR系统或其一部分来记录和再现具有脉冲编码调制的音频信号。 垂直同步信号检测电路包括:输入端子,用于接收包括水平同步信号和垂直同步信号的复合同步信号;输出端,用于提供与垂直同步信号同步的垂直同步脉冲;时钟脉冲发生器电路,连接到 所述输入端子适于产生具有所述水平同步信号的一半周期的时钟脉冲及其四分之一周期的相位滞后;垂直同步信号提取器电路,连接到所述输入端子和所述时钟脉冲发生器电路;以及 适于将垂直同步信号与用于垂直同步信号的参考波形图案进行比较,以便仅当比较导致完全符合时产生与垂直同步信号同步的垂直同步信号,并且垂直同步信号 l补偿电路连接到垂直同步信号提取器电路和时钟脉冲发生器电路,并且响应于垂直同步信号输出以在输出端提供该输出并同时暂时存储,垂直同步信号补偿器电路还适于 当没有接收到垂直同步信号输出时,在输出端提供所存储的垂直同步信号,由此,即使在复合同步信号中缺少垂直同步信号,因此在正确定时产生垂直同步脉冲, 喜欢。
    • 3. 发明授权
    • Error correction method and system
    • 纠错方法和系统
    • US4677622A
    • 1987-06-30
    • US622711
    • 1984-06-20
    • Hiroo OkamotoMasaharu KobayashiKeizo NishimuraTakaharu NoguchiTakao AraiToshifumi Shibuya
    • Hiroo OkamotoMasaharu KobayashiKeizo NishimuraTakaharu NoguchiTakao AraiToshifumi Shibuya
    • G11B20/18G06F11/10
    • G11B20/1809
    • This invention relates to an error correction upon reproduction of digital signals. The error correction is performed by decoding code words such as cross-interleaved Reed Solomon codes, in which first code blocks are formed by a plurality of information words which are in the first arrangement state and a plurality of first check words which are produced by codes associated with the plurality of information words with a Hamming distance of d.sub.1, and second code blocks are formed by a plurality of information words and a plurality of first check words which are in the second arrangement state and which consist of the said plurality of information words and the said plurality of first check words which are respectively included in the different first code blocks, and by a plurality of second check words which are produced by codes associated with the plurality of information words and the plurality of first check words with a Hamming distance of d.sub.2. At the first decoding stage, errors are detected and at the same time the flags indicative of the decoding states are added with respect to the second code blocks. At the second decoding stage, in accordance with the contents of the flags and on the basis of a combination of p.sub.2 and q selected from their combinations satisfying 2p.sub.2 +q.ltoreq.d.sub.1 -1, errors are detected and errors of p.sub.2 words are corrected and erasures of q words to which the flags were added are corrected with respect to the first code blocks.
    • 本发明涉及数字信号再现时的纠错。 通过解码诸如交叉交织的里德·所罗门码的码字来执行纠错,其中第一码块由处于第一布置状态的多个信息字形成,并且由代码产生的多个第一检查字 与具有汉明距离d1的多个信息字相关联,第二码块由处于第二布置状态的多个信息字和多个第一检查词形成,并且由所述多个信息字组成 以及分别包含在不同的第一代码块中的所述多个第一校验字以及由与多个信息字相关联的代码产生的多个第二校验字和具有汉明距离的多个第一校验字 的d2。 在第一解码阶段,检测到错误,并且同时相对于第二代码块添加指示解码状态的标志。 在第二解码阶段,根据标志的内容,并且基于从满足2p2 + q·d1-1的组合中选择的p2和q的组合,检测出错误并校正p2个字的错误 并且相对于第一代码块校正添加了标志的q个字的擦除。
    • 4. 发明授权
    • Digital signal transmission method providing high error correction
capability
    • 数字信号传输方式提供高纠错能力
    • US4649542A
    • 1987-03-10
    • US621743
    • 1984-06-18
    • Keizo NishimuraMasaharu KobayashiHiroo OkamotoTakaharu NoguchiTakao AraiToshifumi Shibuya
    • Keizo NishimuraMasaharu KobayashiHiroo OkamotoTakaharu NoguchiTakao AraiToshifumi Shibuya
    • G11B20/18H03M13/00H03M13/27G06F11/10
    • G11B20/1809
    • A method of transmitting a digital signal in the form of successive signal frames containing codes for detecting and correcting errors of the digital signal for reducing degradation in the quality of the reproduced sound due to generation of the code errors in a digitized audio signal transmission system. An analog signal such as an audio signal is sampled and subjected to A/D conversion. The sample word thus obtained is divided into a plurality of symbol elements. Parity words for detecting and correcting code errors are added to every group of a predetermined number of the information symbols through an interleave procedure before being transmitted. The method includes the steps of applying a first frame of symbols, taken one from each input channel, and having a first arrangement state, to a first error-correcting code encoder to generate a series of first parity words; delaying each of the symbols in the first frame and each of the first parity words by a respective different delay time in a unit of the sample word at a delay line to provide a resulting second frame of symbols in a second arrangement state; applying the second frame of symbols to a second error-correcting code encoder to generate a series of second parity words; and transmitting said second frame of symbols together with said second parity words.
    • 以包含用于检测和校正数字信号的错误的代码的连续信号帧的形式发送数字信号的方法,用于减少由于数字化音频信号传输系统中的代码错误的产生而导致的再现声音质量的劣化。 诸如音频信号的模拟信号被采样并进行A / D转换。 由此获得的采样字被分成多个符号元素。 用于检测和校正码错误的奇偶校验字在发送之前通过交织过程被添加到预定数量的信息符号的每个组中。 该方法包括以下步骤:将第一帧符号从每个输入通道中取出并具有第一布置状态到第一纠错码编码器以产生一系列第一奇偶校验字; 延迟第一帧和第一奇偶校验字中的每个符号以延迟线为单位的采样字的相应的不同延迟时间,以在第二布置状态下提供所得到的第二符号帧; 将第二符号帧应用于第二纠错码编码器以产生一系列第二奇偶校验字; 以及与所述第二奇偶校验字一起发送所述第二符号帧。
    • 5. 发明授权
    • PCM Tape recording and reproducing apparatus having a dropout-immune
data recording format
    • 具有无辍学数据记录格式的PCM磁带记录和再现装置
    • US4539605A
    • 1985-09-03
    • US416244
    • 1982-09-09
    • Takashi HoshinoTakao AraiKeizo Nishimura
    • Takashi HoshinoTakao AraiKeizo Nishimura
    • H03M13/00G11B20/12G11B20/18G11B5/00G11B5/09
    • G11B20/1809
    • A PCM tape recording and reproducing apparatus for recording and reproducing an audio signal by using multitrack heads, comprises a frame interleaving device with a high dropout immunity function. The frame interleaving device comprises a distributor for successively distributing continuous interleaved input data between tracks, wihtin a multiplicity of tracks formed by splitting a magnetic tape, at a spacing of at least one track so that said continuous interleaved input data will not be shared between two continuous tracks in the same recording and reproducing direction, a data framing circuit for forming a frame out of data to be distributed to each of said tracks and for applying said frame with a synchronization signal at the top of said frame and with an error detection code at the end of said frame, and a delay circuit for delaying data associated with a track by one frame or more with respect to data associated with a neighboring track in the same recording and reproducing as said track.
    • 用于通过使用多轨磁头来记录和再现音频信号的PCM磁带记录和再现装置包括具有高压差抗扰度功能的帧交错装置。 帧交织装置包括分配器,用于在轨道之间连续地分配连续的交错输入数据,该多个轨道以至少一个轨道的间隔分割磁带形成,以便所述连续的交错输入数据将不会在两个 在相同的记录和再现方向上的连续轨道,用于从要分配到每个所述轨道的数据形成帧并且用所述帧的顶部具有同步信号来应用所​​述帧的数据成帧电路,并具有错误检测码 在所述帧的结尾,以及延迟电路,用于相对于与所述轨道相同的记录和再现相关于与相邻轨道相关联的数据,将与轨道相关联的数据延迟一帧或更多。
    • 6. 发明授权
    • Circuit and method for protecting a horizontal synchronous signal
    • 用于保护水平同步信号的电路和方法
    • US4420775A
    • 1983-12-13
    • US305779
    • 1981-09-25
    • Shigeru YamazakiTakao AraiMasaharu KobayashiTakashi HoshinoChitoshi HibinoHarukuni Kobari
    • Shigeru YamazakiTakao AraiMasaharu KobayashiTakashi HoshinoChitoshi HibinoHarukuni Kobari
    • H03K5/19H04N5/932H04N5/945G11B27/10G11B5/43
    • H04N5/945H03K5/19H04N5/932
    • A circuit for protecting a horizontal synchronous signal comprises a horizontal synchronous signal detecting circuit responsive to horizontal synchronous pulses included in a composite synchronous signal of a reproduced PCM signal, first and second horizontal synchronous pulse supplementing or adding circuits and an output switching circuit. The output switching circuit operates so that the first supplementing circuit delivers a first supplementary pulse in the absence of a single pulse of the original horizontal synchronous signal, and the second supplementing circuit produces one or more second supplementary pulses in the absence of a plurality of continuous pulses of the original horizontal synchronous signal. When the circuit returns to a condition in which produced horizontal synchronous pulses are synchronous with the original horizontal synchronous pulses, the time interval between adjacent pulses of the original pulses is detected to see whether the interval is either longer or shorter than a predetermined value. As a result, when a pulse first appeared after the returning point is within the predetermined interval, that pulse is removed so that the number of output horizontal synchronous pulses is correct.
    • 用于保护水平同步信号的电路包括水平同步信号检测电路,其响应包括在再现的PCM信号的复合同步信号中的水平同步脉冲,第一和第二水平同步脉冲补充或加法电路以及输出切换电路。 输出切换电路操作,使得第一补充电路在没有原始水平同步信号的单个脉冲的情况下传送第一辅助脉冲,并且第二补充电路在没有多个连续的情况下产生一个或多个第二辅助脉冲 原始水平同步信号的脉冲。 当电路返回到产生的水平同步脉冲与原始水平同步脉冲同步的状态时,检测原始脉冲的相邻脉冲之间的时间间隔,以查看间隔是否比预定值更长或更短。 结果,当在返回点之后首先出现脉冲在预定间隔内时,该脉冲被去除,使得输出水平同步脉冲的数量是正确的。