专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07985714B2 Nb3Sn superconducting wire and precursor therefor 有权
标题翻译： Nb3Sn超导线及其前驱体
公开(公告)号：US07985714B2
公开(公告)日：2011-07-26
申请号：US11902471
申请日：2007-09-21
申请人： Hiroyuki Kato , Takashi Hase , Kyoji Zaitsu
发明人： Hiroyuki Kato , Takashi Hase , Kyoji Zaitsu
IPC分类号： H01B12/00 , H01L39/24
CPC分类号： H01L39/2409 , Y10S420/901 , Y10S428/93 , Y10S505/887 , Y10T29/49014 , Y10T428/12819
摘要： A precursor for fabricating a Nb3Sn superconducting wire by an internal Sn process includes one or a plurality of stabilizing copper portions collectively disposed in the center, each stabilizing copper portion being provided with a diffusion barrier layer in the periphery thereof, and a superconducting matrix portion disposed so as to surround the one or the plurality of stabilizing copper portions, the superconducting matrix portion including a Nb or Nb-based alloy core and a Sn or Sn-based alloy core embedded in a Cu or Cu-based alloy matrix.
摘要翻译：通过内部Sn工艺制造Nb 3 Sn超导线的前体包括一个或多个稳定的铜部分，其集中设置在中心，每个稳定的铜部分在其周边设置有扩散阻挡层，并且设置超导矩阵部分围绕一个或多个稳定化铜部分，超导矩阵部分包括Nb或Nb基合金芯和嵌入Cu或Cu基合金基体中的Sn或Sn基合金芯。

2. 发明申请

US20080287303A1 Nb3Sn superconducting wire, precursor or same, and method for producing precursor 审中-公开
标题翻译： Nb3Sn超导线，前驱体等，以及前体的制造方法
公开(公告)号：US20080287303A1
公开(公告)日：2008-11-20
申请号：US12081475
申请日：2008-04-16
申请人： Hiroyuki Kato , Takashi Hase , Kyoji Zaitsu
发明人： Hiroyuki Kato , Takashi Hase , Kyoji Zaitsu
IPC分类号： H01B12/10 , H01L39/24 , H01B12/00
CPC分类号： H01L39/2409 , H01L39/14 , Y10T29/49014
摘要： A precursor for producing a Nb3Sn superconducting wire includes a bundle of single-element wires each including a Cu or Cu-based alloy matrix, Nb or Nb-based alloy filaments, at least one Sn or Sn-based alloy core, the Nb or Nb-based alloy filaments and at least one Sn or Sn-based alloy core being arranged in the Cu or Cu-based alloy matrix, an diffusion barrier layer around the periphery of the Cu or Cu-based alloy matrix, the inner diffusion barrier layer being composed of Nb or a Nb-based alloy, and a Cu or Cu-based alloy layer around the periphery of the diffusion barrier layer; an outer diffusion barrier layer around the periphery of the bundle of the single-element wires, the outer diffusion barrier layer being composed of Nb, a Nb-based alloy, Ta, a Ta-based alloy, or a combination thereof; and a stabilizing copper layer around the periphery of the outer diffusion barrier layer.
摘要翻译：用于制造Nb 3 Sn超导线的前体包括：包含Cu或Cu基合金基体，Nb或Nb基合金细丝，至少一种Sn或Sn的单元线束基于Nb或Nb的合金芯，并且在Cu或Cu基合金基体中布置有至少一种Sn或Sn基合金芯，围绕Cu或Cu基合金芯的周围的扩散阻挡层合金基体，内扩散阻挡层由Nb或Nb基合金构成，以及在扩散阻挡层周围的Cu或Cu基合金层; 所述外部扩散阻挡层围绕所述单个元件线束的周围，所述外部扩散阻挡层由Nb，Nb基合金，Ta，Ta基合金或其组合构成; 以及围绕外部扩散阻挡层的周边的稳定的铜层。

3. 发明申请

US20070163675A1 Nb3Sn superconducting wire and precursor for the same 审中-公开
标题翻译： Nb3Sn超导线及前驱体相同
公开(公告)号：US20070163675A1
公开(公告)日：2007-07-19
申请号：US11593541
申请日：2006-11-07
申请人： Takashi Hase , Yukinobu Murakami , Hiroyuki Yasunaka , Takayoshi Miyazaki , Hiroyuki Kato , Kyoji Zaitsu
发明人： Takashi Hase , Yukinobu Murakami , Hiroyuki Yasunaka , Takayoshi Miyazaki , Hiroyuki Kato , Kyoji Zaitsu
IPC分类号： H01L39/24
CPC分类号： H01L39/2409
摘要： A precursor for manufacturing a Nb3Sn superconducting wire by bronze method, in which plural Nb or Nb-based alloy cores are buried in a Cu—Sn-based alloy base material. The Cu—Sn-based alloy base material comprises Ti and/or Zr in addition to Sn, and these components satisfy the equations (1) and (2) below: 0.4≦(X−15.6)/Y≦1.9 (1) and 15.6
摘要翻译：通过青铜法制造Nb 3 O 3 Sn超导线的前体，其中多个Nb或Nb基合金芯埋在Cu-Sn基合金基材中。除了Sn之外，Cu-Sn系合金基材还含有Ti和/或Zr，这些成分满足下述式（1）和（2）：＆lt;线内配方说明=“在线式” end =“lead”？> 0.4 <=（X-15.6）/ Y <= 1.9（1）<？in-line-formula description =“In-line Formulas”end =“tail”？> <？in-line -formulae description =“In-line Formulas”end =“lead”？>和<？in-line-formula description =“In-line Formulas”end =“tail”？> <？in-line-formula description =“ 在线公式“end =”lead“？> 15.6 其中符号X表示内容的Sn质量％，符号Y表示Ti和Zr的质量％的总含量。

4. 发明申请

US20080167192A1 Nb3Sn superconducting wire and precursor therefor 有权
标题翻译： Nb3Sn超导线及其前驱体
公开(公告)号：US20080167192A1
公开(公告)日：2008-07-10
申请号：US11902471
申请日：2007-09-21
申请人： Hiroyuki Kato , Takashi Hase , Kyoji Zaitsu
发明人： Hiroyuki Kato , Takashi Hase , Kyoji Zaitsu
IPC分类号： H01B12/00
CPC分类号： H01L39/2409 , Y10S420/901 , Y10S428/93 , Y10S505/887 , Y10T29/49014 , Y10T428/12819
摘要： A precursor for fabricating a Nb3Sn superconducting wire by an internal Sn process includes one or a plurality of stabilizing copper portions collectively disposed in the center, each stabilizing copper portion being provided with a diffusion barrier layer in the periphery thereof, and a superconducting matrix portion disposed so as to surround the one or the plurality of stabilizing copper portions, the superconducting matrix portion including a Nb or Nb-based alloy core and a Sn or Sn-based alloy core embedded in a Cu or Cu-based alloy matrix.
摘要翻译：通过内部Sn工艺制造Nb 3 Sn超导线的前体包括一个或多个稳定的铜部分集中设置在中心，每个稳定的铜部分在其中设置有扩散阻挡层周边，以及包围一个或多个稳定化铜部分的超导矩阵部分，所述超导矩阵部分包括Nb或Nb基合金芯和嵌在Cu中的Sn或Sn基合金芯，或铜基合金基体。

5. 发明授权

US07781319B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07781319B2
公开(公告)日：2010-08-24
申请号：US12048265
申请日：2008-03-14
申请人： Takashi Hase
发明人： Takashi Hase
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/336 , H01L21/8234
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： According to the present invention, it is provided a method of manufacturing a semiconductor device comprising a PMOS transistor and a NMOS transistor, wherein the method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.
摘要翻译：根据本发明，提供一种制造包括PMOS晶体管和NMOS晶体管的半导体器件的方法，其中该方法分别有助于获得用于NMOS晶体管和PMOS晶体管的合适组成的FUSI相，具有较少的掩模层数和数量较少的制造步骤。

6. 发明申请

US20090267158A1 SEMICONDUCTOR DEVICE AND MANUFACTURING PROCESS THEREFOR 有权
标题翻译：半导体器件及其制造工艺
公开(公告)号：US20090267158A1
公开(公告)日：2009-10-29
申请号：US12094755
申请日：2006-11-21
申请人： Takashi Hase
发明人： Takashi Hase
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28097 , H01L21/823871 , H01L29/4975 , H01L29/66545
摘要： There is provided a semiconductor device in which deviation in a work function is prevented by a gate electrode having a uniform composition and which has excellent operation properties by effectively controlling a Vth. The semiconductor device comprises an NMOS transistor and a PMOS transistor with a common line electrode, characterized in that the line electrode comprise an electrode section (A), an electrode section (B) and a diffusion barrier region formed in a part over an isolation region so that the electrode sections (A) and (B) are kept out of contact and the diffusion barrier region meets at least one of the following conditions (1) and (2). (1) The diffusion coefficient D1 in the above diffusion barrier region of the constituent element A′ of the above electrode section (A) is lower than the interdiffusion coefficient D2 of the constituent element A′ between electrode section (A) materials. (2) The diffusion coefficient D3 in the above diffusion barrier region of the constituent element B′ of the above electrode section (B) is lower than the interdiffusion coefficient D4 of the constituent element B′ between electrode section (B) materials.
摘要翻译：提供了一种半导体器件，通过有效地控制Vth，通过具有均匀组成的栅电极防止功函中的偏差，并且具有优异的操作特性。半导体器件包括NMOS晶体管和具有公共线电极的PMOS晶体管，其特征在于，线电极包括电极部分（A），电极部分（B）和形成在隔离区域上的部分中的扩散阻挡区域使得电极部分（A）和（B）保持不接触，并且扩散阻挡区域满足以下条件（1）和（2）中的至少一个。（1）上述电极部（A）的构成元素A'的扩散阻挡区域的扩散系数D1低于电极部（A）材料之间的构成元素A'的相互扩散系数D2。（2）上述电极部（B）的构成元件B'的扩散阻挡区域的扩散系数D3低于电极部（B）材料之间的构成元件B'的相互扩散系数D4。

7. 发明授权

US06440751B1 Method of manufacturing thin film and thin film capacitor 有权
标题翻译：制造薄膜和薄膜电容器的方法
公开(公告)号：US06440751B1
公开(公告)日：2002-08-27
申请号：US09653141
申请日：2000-08-31
申请人： Takashi Hase
发明人： Takashi Hase
IPC分类号： H01L2100
CPC分类号： C23C18/1225 , C23C18/1216 , C23C18/1283 , C23C18/1295 , H01L21/31691 , H01L28/56
摘要： In a method of manufacturing a thin film, a buffer layer is formed a substrate. Thereafter, a ferroelectric thin film material is applied thereto before thermally decomposing the buffer layer. Subsequently, the buffer layer and the ferroelectric thin film are decomposed together. Finally, a crystallized thermal process is performed.
摘要翻译：在制造薄膜的方法中，缓冲层形成为基板。此后，在热分解缓冲层之前施加铁电薄膜材料。随后，缓冲层和铁电薄膜一起分解。最后，进行结晶热处理。

8. 发明授权

US06194227B1 Method of producing a bismuth layer structured ferroelectric thin film 有权
标题翻译：生产铋层结构铁电薄膜的方法
公开(公告)号：US06194227B1
公开(公告)日：2001-02-27
申请号：US09174393
申请日：1998-10-14
申请人： Takashi Hase
发明人： Takashi Hase
IPC分类号： H01L2100
CPC分类号： H01L21/31691 , H01L28/56
摘要： The surface of a Si substrate is coated with a lower electrode of precious metal (Pt), then a buffer layer comprising an oxide thin film containing Bi is deposited. On the surface of the buffer layer, a thin film of a Bi layer structured ferroelectric substance is formed. Thus, reaction of the Bi layer structured ferroelectric substance with the precious metal coating the Si substrate is avoided during crystallization carried out at a low temperature. Therefore, deviation in composition of the thin film thus formed is suppressed to provide the thin film with a high density. When the thickness of the buffer layer is not greater than five percent of that of the Bi layer structured ferroelectric thin film, electrical characteristics of a capacitor are not deteriorated. When electrical connection is conducted by polycrystalline Si, production of oxide can be avoided by deposition at 650° C.
摘要翻译： Si衬底的表面涂覆有贵金属（Pt）的下电极，然后沉积包含含有Bi的氧化物薄膜的缓冲层。在缓冲层的表面形成有Bi层结构的铁电体的薄膜。因此，在低温下进行结晶时避免了Bi层结构的铁电体与覆盖Si衬底的贵金属的反应。因此，抑制如此形成的薄膜的组成偏差，从而提供高密度的薄膜。当缓冲层的厚度不大于Bi层结构的铁电薄膜的厚度的5％时，电容器的电特性不会劣化。当通过多晶硅进行电连接时，可以通过在650℃下沉积来避免生成氧化物。

9. 发明授权

US5421890A Apparatus for producing oxide thin film 失效
标题翻译：氧化物薄膜的制造装置
公开(公告)号：US5421890A
公开(公告)日：1995-06-06
申请号：US98903
申请日：1993-07-29
申请人： Ryusuke Kita , Takashi Hase , Masato Sasaki , Tadataka Morishita
发明人： Ryusuke Kita , Takashi Hase , Masato Sasaki , Tadataka Morishita
IPC分类号： C23C8/12 , C04B41/50 , C04B41/85 , C04B41/87 , C23C8/16 , C23C14/08 , C23C14/24 , C23C14/58 , C30B23/02 , C23C16/40
CPC分类号： C04B41/009 , C04B41/5027 , C04B41/5072 , C04B41/85 , C04B41/87 , C23C14/08 , C23C14/24 , C30B23/002 , C30B23/02 , C30B29/16 , C30B29/22
摘要： Disclosed is an oxide thin film producing method and apparatus for producing an oxide thin film having excellent crystallinity and purity with high productivity while correctly controlling the composition of the oxide thin film. After reducing the pressure inside a vacuum chamber to 1.times.10.sup.-9 Torr or less, a metal thin film is formed by evaporating a specified metal element and depositing vapor of the metal element on a substrate in the vacuum chamber. Then a cover member is moved upward to closely abut to a cover receiving member to thereby form an airtight chamber for enclosing the substrate airtightly in the vacuum chamber. With the degree of vacuum around the airtight chamber maintained, O.sub.2 gas is directly introduced into the airtight chamber through a gas piping to oxidize the metal thin film and thereby form an oxide thin film. At the same time, the gas inside the airtight chamber is discharged directly out of the vacuum chamber through a gas piping.
摘要翻译：公开了一种用于在正确控制氧化物薄膜的组成的同时以高生产率制造具有优异的结晶度和纯度的氧化物薄膜的氧化物薄膜制造方法和装置。在将真空室内的压力降低到1×10 -9 Torr或更小之后，通过蒸发特定的金属元素并将金属元素的蒸气沉积在真空室中的基底上来形成金属薄膜。然后，盖构件向上移动以紧密地邻接到盖接收构件，从而形成用于将基底气密地封闭在真空室中的气密室。随着保持气密室周围的真空度，通过气体管道将O2气体直接引入气密室，以氧化金属薄膜，从而形成氧化物薄膜。同时，气密室内的气体通过气体管道直接排出真空室外。

10. 发明授权

US5231328A Phosphor and ultraviolet ray excited fluorescent tube employing it 失效
标题翻译：使用荧光粉和紫外线激发荧光灯管
公开(公告)号：US5231328A
公开(公告)日：1993-07-27
申请号：US899157
申请日：1992-06-15
申请人： Takayuki Hisamune , Takashi Hase
发明人： Takayuki Hisamune , Takashi Hase
IPC分类号： C09K11/77 , H01J61/44
CPC分类号： H01J61/44 , C09K11/774
摘要： A bivalent europium-activated alkaline earth haloborate phosphor which contains lithium as coactivator, a process for its production, and an ultraviolet ray excited fluorescent tube such as a fluorescent lamp having a fluorescent layer containing such a phosphor as the blue-emitting component.
摘要翻译：含有锂作为共激活剂的二价铕活化碱土金属卤硼酸盐荧光体，其制造方法，以及荧光灯等紫外线激发荧光管，其荧光层含有蓝色发光成分的荧光体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式