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1. 发明授权

US08918654B2 Information processing device, program verification method, and recording medium 有权
标题翻译：信息处理装置，程序验证方法和记录介质
公开(公告)号：US08918654B2
公开(公告)日：2014-12-23
申请号：US12274024
申请日：2008-11-19
申请人： Mikio Hashimoto , Hiroyoshi Haruki , Yurie Fujimatsu , Takeshi Kawabata
发明人： Mikio Hashimoto , Hiroyoshi Haruki , Yurie Fujimatsu , Takeshi Kawabata
IPC分类号： G06F15/16 , G06F12/14 , G06F21/54
CPC分类号： G06F12/1416 , G06F21/54
摘要： A first storage unit stores a plurality of security functions each defining a first protection attribute requiring a storage of a value of an argument for input/output of data. A second storage unit stores a program list describing a second protection attribute of a variable indicating a storage area of the data and an executing procedure of a predetermined process. An identifying unit identifies a third protection attribute of an actual argument for input/output of a security function based on the second protection attribute. When a judging unit judges not all of third protection attributes match with first protection attributes, an output unit outputs error information indicating a mismatch of the protection attributes.
摘要翻译：第一存储单元存储多个安全功能，每个安全功能定义需要存储数据值以输入/输出数据的第一保护属性。第二存储单元存储描述指示数据的存储区域的变量的第二保护属性的程序列表和预定处理的执行过程。识别单元基于第二保护属性识别安全功能的输入/输出的实际参数的第三保护属性。当判断单元判断不是所有第三保护属性与第一保护属性匹配时，输出单元输出指示保护属性不匹配的错误信息。

2. 发明授权

US08499306B2 Microprocessor configured to control a process in accordance with a request based on task identification information and the register information identifier 失效
标题翻译：微处理器被配置为根据基于任务识别信息和寄存器信息标识符的请求来控制进程
公开(公告)号：US08499306B2
公开(公告)日：2013-07-30
申请号：US12926251
申请日：2010-11-04
申请人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
发明人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
IPC分类号： G06F9/46 , G06F9/44
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30123 , G06F9/485
摘要： A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.
摘要翻译：微处理器执行流水线架构中的程序，其包括任务寄存器管理单元，该任务寄存器管理单元将任务寄存器的值切换到在完成第一任务的执行之后执行第二任务时所使用的第二寄存器信息，如果切换指令当多个单元执行第一任务时发出第二任务;以及任务管理器，其在将值切换到第二登记信息之后将任务识别信息寄存器的值切换到第二任务标识符，并且授予每个多个单元允许执行第二任务。

3. 发明授权

US08191155B2 Microprocessor 有权
标题翻译：微处理器
公开(公告)号：US08191155B2
公开(公告)日：2012-05-29
申请号：US11060704
申请日：2005-02-18
申请人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
发明人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
IPC分类号： H04L29/06
CPC分类号： G06F11/3648
摘要： A microprocessor having a processor core includes an information acquisition unit that acquires information encrypted to be used by the processor core, from outside; a decryption unit that decrypts the information with a symmetric key to obtain plain text; and a controller that controls processing on the information acquired by the information acquisition unit based on the symmetric key.
摘要翻译：具有处理器核心的微处理器包括信息获取单元，从外部获取加密以供处理器核心使用的信息; 解密单元，用对称密钥解密信息以获得明文; 以及控制器，其基于所述对称密钥来控制对由所述信息获取单元获取的信息的处理。

4. 发明授权

US07707645B2 Microprocessor 失效
标题翻译：微处理器
公开(公告)号：US07707645B2
公开(公告)日：2010-04-27
申请号：US11159230
申请日：2005-06-23
申请人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
发明人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
IPC分类号： G06F7/04 , G06F17/30 , H04N7/16
CPC分类号： G06F21/57
摘要： A microprocessor includes a decryption unit that decrypts information to be utilized by a processor core to obtain plaintext information when the acquired information is encrypted; and a plaintext information storing unit that stores the plaintext information. The microprocessor also includes a protected attribute adding unit that adds a protected attribute indicating one of protection and non-protection to the plaintext information based on whether the decryption has been performed; an access request acquiring unit that acquires an access request to the plaintext information; a request type identifying unit that identifies a type of request of the access request; and an access controlling unit that controls an access to the plaintext information based on the type of request and the protected attribute.
摘要翻译：微处理器包括一个解密单元，当所获取的信息被加密时，解密由处理器核心利用的信息以获取明文信息; 以及存储明文信息的明文信息存储单元。微处理器还包括受保护属性添加单元，该保护属性添加单元基于是否执行了解密，向明文信息添加指示保护和非保护之一的受保护属性; 访问请求获取单元，其获取对所述明文信息的访问请求; 识别访问请求的请求的类型的请求类型识别单元; 以及访问控制单元，其基于请求的类型和所保护的属性来控制对明文信息的访问。

5. 发明授权

US09116741B2 Computer program product, and information processing apparatus and method 有权
标题翻译：计算机程序产品，信息处理设备和方法
公开(公告)号：US09116741B2
公开(公告)日：2015-08-25
申请号：US13585941
申请日：2012-08-15
申请人： Hiroyoshi Haruki , Mikio Hashimoto , Fukutomo Nakanishi , Ryotaro Hayashi , Yurie Fujimatsu , Tomohide Jokan , Takeshi Kawabata
发明人： Hiroyoshi Haruki , Mikio Hashimoto , Fukutomo Nakanishi , Ryotaro Hayashi , Yurie Fujimatsu , Tomohide Jokan , Takeshi Kawabata
IPC分类号： H04L9/00 , G06F11/00 , G06F9/46 , G06F21/52
CPC分类号： G06F9/461 , G06F21/52
摘要： According to an embodiment, a computer program product includes a computer-readable medium including program, when executed by a computer, to have a plurality of modules run by the computer. The computer includes a memory having a shared area, which is an area accessible to only those modules which run cooperatively and storing therein execution module identifiers. Each of the modules includes a first operation configured to store, just prior to a switchover of operations to an other module that runs cooperatively, an identifier of the other module as the execution module identifier in the shared area; and a second operation configured to execute, when the execution module identifier stored in the shared area matches with an identifier of own module immediately after a switchover of operations from the other module, a function inside the own module.
摘要翻译：根据实施例，计算机程序产品包括计算机可读介质，其包括由计算机执行时具有由计算机运行的多个模块的程序。计算机包括具有共享区域的存储器，该共享区域是只能协作运行并在其中存储执行模块标识符的那些模块可访问的区域。每个模块包括第一操作，其被配置为在操作切换到协同运行的其他模块之前存储另一模块的标识符作为共享区域中的执行模块标识符; 以及第二操作，被配置为当存储在所述共享区域中的执行模块标识符与来自所述另一模块的操作的切换之后立即匹配自身模块的标识符时，执行所述自身模块内的功能。

6. 发明授权

US08732480B2 Memory management device and memory management method 有权
标题翻译：内存管理设备和内存管理方法
公开(公告)号：US08732480B2
公开(公告)日：2014-05-20
申请号：US13223753
申请日：2011-09-01
申请人： Mikio Hashimoto , Hiroyoshi Haruki , Takeshi Kawabata , Tomohide Jokan , Yurie Fujimatsu , Ryotaro Hayashi , Fukutomo Nakanishi
发明人： Mikio Hashimoto , Hiroyoshi Haruki , Takeshi Kawabata , Tomohide Jokan , Yurie Fujimatsu , Ryotaro Hayashi , Fukutomo Nakanishi
IPC分类号： G06F17/30
CPC分类号： G06F12/1425 , G06F21/52 , G06F21/64
摘要： According to an embodiment, a memory management device increments a lower value of a first counter, updates the counter by incrementing an upper value and resetting the lower value when the lower value overflows, increments to update the lower counter value when the upper value is incremented as a result of writing a second data piece having the upper value in common to a memory, recalculates a first secret value calculated using the first counter values and a root secret value in response to the first counter update, writes a first data piece and the first secret value to the memory, and at reading of the first data piece and the first secret value, calculates a second secret value using the updated first counter values and the root secret value, and compares the first secret value with the second secret value to verify the first data piece.
摘要翻译：根据实施例，存储器管理装置增加第一计数器的较低值，通过递增上限值来更新计数器，并且当较低值溢出时重新设置较低值，当增加上限值时递增以更新下计数器值作为将具有上述值的第二数据片共同写入存储器的结果，重新计算响应于第一计数器更新使用第一计数器值和根秘密值计算的第一秘密值，写入第一数据片和并且在读取第一数据段和第一秘密值时，使用更新的第一计数器值和根秘密值计算第二秘密值，并将第一秘密值与第二秘密值比较，验证第一个数据。

7. 发明授权

US07853954B2 Method and apparatus for preserving the context of tasks during task switching in a pipeline architecture 有权
标题翻译：在流水线架构中任务切换期间保留任务上下文的方法和装置
公开(公告)号：US07853954B2
公开(公告)日：2010-12-14
申请号：US11175296
申请日：2005-07-07
申请人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
发明人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
IPC分类号： G06F9/46 , G06F9/44
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30123 , G06F9/485
摘要： A microprocessor executes programs in a pipeline architecture including a task register management unit that, if a switch instruction to a second task is issued when a plurality of units executes a first task, switches a value of a task register to second register information that is used when the second task is executed after the execution of the first task is completed and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.
摘要翻译：微处理器执行流水线架构中的程序，包括任务寄存器管理单元，当多个单元执行第一任务时，如果发出第二任务的切换指令，则将任务寄存器的值切换到所使用的第二寄存器信息当在完成第一任务的执行之后执行第二任务时，以及任务管理器，其在该值被切换到第二登记器信息之后将任务识别信息寄存器的值切换到第二任务标识符，并且授予每个多个单元允许执行第二任务。

8. 发明申请

US20090138729A1 INFORMATION PROCESSING DEVICE, PROGRAM VERIFICATION METHOD, AND RECORDING MEDIUM 有权
标题翻译：信息处理设备，程序验证方法和记录介质
公开(公告)号：US20090138729A1
公开(公告)日：2009-05-28
申请号：US12274024
申请日：2008-11-19
申请人： Mikio Hashimoto , Hiroyoshi Haruki , Yurie Fujimatsu , Takeshi Kawabata
发明人： Mikio Hashimoto , Hiroyoshi Haruki , Yurie Fujimatsu , Takeshi Kawabata
IPC分类号： G06F12/14
CPC分类号： G06F12/1416 , G06F21/54
摘要： A first storage unit stores a plurality of security functions each defining a first protection attribute requiring a storage of a value of an argument for input/output of data. A second storage unit stores a program list describing a second protection attribute of a variable indicating a storage area of the data and an executing procedure of a predetermined process. An identifying unit identifies a third protection attribute of an actual argument for input/output of a security function based on the second protection attribute. When a judging unit judges not all of third protection attributes match with first protection attributes, an output unit outputs error information indicating a mismatch of the protection attributes.
摘要翻译：第一存储单元存储多个安全功能，每个安全功能定义需要存储数据值以输入/输出数据的第一保护属性。第二存储单元存储描述指示数据的存储区域的变量的第二保护属性的程序列表和预定处理的执行过程。识别单元基于第二保护属性识别安全功能的输入/输出的实际参数的第三保护属性。当判断单元判断不是所有第三保护属性与第一保护属性匹配时，输出单元输出指示保护属性不匹配的错误信息。

9. 发明申请

US20050289397A1 Microprocessor 有权
标题翻译：微处理器
公开(公告)号：US20050289397A1
公开(公告)日：2005-12-29
申请号：US11060704
申请日：2005-02-18
申请人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
发明人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
IPC分类号： G06F11/00
CPC分类号： G06F11/3648
摘要： A microprocessor having a processor core includes an information acquisition unit that acquires information encrypted to be used by the processor core, from outside; a decryption unit that decrypts the information with a symmetric key to obtain plain text; and a controller that controls processing on the information acquired by the information acquisition unit based on the symmetric key.
摘要翻译：具有处理器核心的微处理器包括信息获取单元，从外部获取加密以供处理器核心使用的信息; 解密单元，用对称密钥解密信息以获得明文; 以及控制器，其基于所述对称密钥来控制对由所述信息获取单元获取的信息的处理。

10. 发明申请

US20060010308A1 Microprocessor 有权
标题翻译：微处理器
公开(公告)号：US20060010308A1
公开(公告)日：2006-01-12
申请号：US11175296
申请日：2005-07-07
申请人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
发明人： Hiroyoshi Haruki , Mikio Hashimoto , Takeshi Kawabata
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30123 , G06F9/485
摘要： A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.
摘要翻译：微处理器执行流水线架构中的程序，其包括任务寄存器管理单元，该任务寄存器管理单元将任务寄存器的值切换到在完成第一任务的执行之后执行第二任务时所使用的第二寄存器信息，如果切换指令当多个单元执行第一任务时发出第二任务;以及任务管理器，其在将值切换到第二登记信息之后将任务识别信息寄存器的值切换到第二任务标识符，并且授予每个多个单元允许执行第二任务。

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