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    • 4. 发明授权
    • Microprocessor
    • 微处理器
    • US07707645B2
    • 2010-04-27
    • US11159230
    • 2005-06-23
    • Hiroyoshi HarukiMikio HashimotoTakeshi Kawabata
    • Hiroyoshi HarukiMikio HashimotoTakeshi Kawabata
    • G06F7/04G06F17/30H04N7/16
    • G06F21/57
    • A microprocessor includes a decryption unit that decrypts information to be utilized by a processor core to obtain plaintext information when the acquired information is encrypted; and a plaintext information storing unit that stores the plaintext information. The microprocessor also includes a protected attribute adding unit that adds a protected attribute indicating one of protection and non-protection to the plaintext information based on whether the decryption has been performed; an access request acquiring unit that acquires an access request to the plaintext information; a request type identifying unit that identifies a type of request of the access request; and an access controlling unit that controls an access to the plaintext information based on the type of request and the protected attribute.
    • 微处理器包括一个解密单元,当所获取的信息被加密时,解密由处理器核心利用的信息以获取明文信息; 以及存储明文信息的明文信息存储单元。 微处理器还包括受保护属性添加单元,该保护属性添加单元基于是否执行了解密,向明文信息添加指示保护和非保护之一的受保护属性; 访问请求获取单元,其获取对所述明文信息的访问请求; 识别访问请求的请求的类型的请求类型识别单元; 以及访问控制单元,其基于请求的类型和所保护的属性来控制对明文信息的访问。
    • 5. 发明授权
    • Microprocessor with improved task management and table management mechanism
    • 微处理器具有改进的任务管理和表管理机制
    • US07673155B2
    • 2010-03-02
    • US12118291
    • 2008-05-09
    • Mikio HashimotoKensaku FujimotoKenji Shirakawa
    • Mikio HashimotoKensaku FujimotoKenji Shirakawa
    • H04L9/32
    • G06F21/72G06F21/123G06F21/126G06F2221/2107
    • A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when the task identifier in the tag and the value of the task register do not coincide.
    • 防篡改微处理器具有任务状态表,用于将任务标识符分配给可以采取多种状态的任务,并且存储对应于任务标识符的任务状态; 用于存储当前执行的任务的任务标识符的任务寄存器; 当进行任务请求时,以高速缓存线为单位读取以外部存储器上的程序密钥加密的形式存储的程序的接口; 加密处理单元,用于根据程序密钥生成不同的高速缓存行不同的解密密钥,并解密由界面读取的内容; 由多个高速缓存行形成的高速缓冲存储器,每个高速缓存行均具有标签,用于存储对应于在每个高速缓存行的标签中对每个高速缓存行进行解密中使用的解密密钥相对应的任务标识符; 以及访问检查单元,用于将存储在每个高速缓存行的标签中的任务标识符与任务寄存器的值进行比较,并且当标签中的任务标识符和任务寄存器的值不为止时,丢弃每个高速缓存行的内容 重合。
    • 6. 发明授权
    • Microprocessor with improved task management and table management mechanism
    • 微处理器具有改进的任务管理和表管理机制
    • US07424622B2
    • 2008-09-09
    • US10259379
    • 2002-09-30
    • Mikio HashimotoKensaku FujimotoKenji Shirakawa
    • Mikio HashimotoKensaku FujimotoKenji Shirakawa
    • H04L9/32
    • G06F21/72G06F21/123G06F21/126G06F2221/2107
    • A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when the task identifier in the tag and the value of the task register do not coincide.
    • 防篡改微处理器具有任务状态表,用于将任务标识符分配给可以采取多种状态的任务,并且存储对应于任务标识符的任务状态; 用于存储当前执行的任务的任务标识符的任务寄存器; 当进行任务请求时,以高速缓存线为单位读取以外部存储器上的程序密钥加密的形式存储的程序的接口; 加密处理单元,用于根据程序密钥生成不同的高速缓存行不同的解密密钥,并解密由界面读取的内容; 由多个高速缓存行形成的高速缓冲存储器,每个高速缓存行均具有标签,用于存储对应于在每个高速缓存行的标签中对每个高速缓存行进行解密中使用的解密密钥相对应的任务标识符; 以及访问检查单元,用于将存储在每个高速缓存行的标签中的任务标识符与任务寄存器的值进行比较,并且当标签中的任务标识符和任务寄存器的值不为止时,丢弃每个高速缓存行的内容 重合。
    • 7. 发明申请
    • Processor having program protection function
    • 处理器具有程序保护功能
    • US20070050619A1
    • 2007-03-01
    • US11353178
    • 2006-02-14
    • Takashi MiyamoriMikio Hashimoto
    • Takashi MiyamoriMikio Hashimoto
    • H04L9/00
    • G06F21/71G06F9/30181G06F9/3802G06F11/3636
    • A processor having a program protection function, which makes behavior analysis of protected programs difficult and allows improvement in the current program protection level, which is attained by prohibiting reading out/rewriting of instruction codes, is provided. The processor having a program protection function is a processor core module, which protects programs by allowing only reading out of instructions in a decrypted, protected plain text program for being executed and which is constituted by a detecting unit for detecting whether or not an instruction in a protected program is being executed and a prohibiting unit for prohibiting generation of trace information for an instruction being executed when the detecting unit detects that an instruction in a protected program is being executed.
    • 提供了具有程序保护功能的处理器,其使得受保护程序的行为分析变得困难并且允许通过禁止读取/重写指令代码而获得的当前程序保护级别的改进。 具有程序保护功能的处理器是处理器核心模块,其通过仅读取解密的受保护的明文程序中的指令来保护程序,用于执行,并且由检测单元构成,用于检测是否执行指令 正在执行受保护的程序,以及禁止单元,用于当检测单元检测到正在执行受保护程序中的指令时,禁止产生正在执行的指令的跟踪信息。