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1. 发明申请

US20120079167A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20120079167A1
公开(公告)日：2012-03-29
申请号：US13038681
申请日：2011-03-02
申请人： Hiroshi YAO , Shinichi KANNO , Kazuhiro FUKUTOMI
发明人： Hiroshi YAO , Shinichi KANNO , Kazuhiro FUKUTOMI
IPC分类号： G06F12/00
CPC分类号： G06F3/0604 , G06F3/0634 , G06F3/0641 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F2212/1016 , G06F2212/1024 , G06F2212/1044 , G06F2212/214 , G06F2212/7201 , G06F2212/7205
摘要： According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
摘要翻译：根据一个实施例，存储器系统包括非易失性半导体存储器，块管理单元和转录单元。半导体存储器包括能够在第一模式和第二模式中写入数据的多个块。块管理单元管理其中没有有效数据作为空闲块的块。当由块管理单元管理的空闲块的数量小于或等于预定阈值时，转录单元选择一个或多个使用存储有效数据的块作为转录源块并转录存储在转录源中的有效数据在第二种模式下阻止空闲块。

2. 发明申请

US20110060863A1 CONTROLLER 有权
标题翻译：控制器
公开(公告)号：US20110060863A1
公开(公告)日：2011-03-10
申请号：US12716547
申请日：2010-03-03
申请人： Tetsuro KIMURA , Shinichi KANNO , Shigehiro ASANO , Kazuhiro FUKUTOMI
发明人： Tetsuro KIMURA , Shinichi KANNO , Shigehiro ASANO , Kazuhiro FUKUTOMI
IPC分类号： G06F12/00 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F2212/7201 , G06F2212/7205
摘要： A controller stores therein a sector address set indicating logical storage positions within a nonvolatile-memory storage area; page addresses indicating, in units of pages, physical storage positions within the nonvolatile-memory storage area; and pieces of management information each indicating whether one or more special sectors each being either a bad sector or a trimmed sector trimmed by a TRIM command are present in the corresponding page, while associating them with each other. When an access to a specified sector address is requested, the device refers to the piece of management information and judges whether any special sector is present in the page identified by the page address corresponding to the sector address. The device generates predetermined response data if the page contains one or more special sectors and accesses the nonvolatile-memory storage position corresponding to the sector address if the page contains no special sector.
摘要翻译：控制器在其中存储指示非易失性存储器存储区域内的逻辑存储位置的扇区地址集合; 页面地址，以页为单位指示非易失性存储器存储区域内的物理存储位置; 以及各管理信息，每个管理信息指示在相应的页面中是否存在各自为坏扇区的一个或多个特殊扇区或由TRIM命令修剪的修剪扇区，同时将它们相互关联。当请求对指定的扇区地址的访问时，设备参考管理信息，并判断由扇区地址对应的页地址所标识的页面中是否存在特殊扇区。如果页面包含一个或多个特殊扇区，则该设备产生预定的响应数据，并且如果页面不包含特殊扇区，则访问对应于扇区地址的非易失性存储器存储位置。

3. 发明申请

US20130246688A1 SEMICONDUCTOR MEMORY DEVICE AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：半导体存储器件和计算机程序产品
公开(公告)号：US20130246688A1
公开(公告)日：2013-09-19
申请号：US13586219
申请日：2012-08-15
申请人： Shinichi KANNO , Kazuhiro FUKUTOMI
发明人： Shinichi KANNO , Kazuhiro FUKUTOMI
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： According an embodiment, a semiconductor memory device includes a semiconductor memory chip to store plural pieces of data that are written and read in units of a page and are erased in units of a block including plural pages; a discarding unit to discard, after the data is written in the semiconductor memory chip with a logic address being designated, at least a portion of valid data among the plural pieces of data; a compaction unit to write the valid data excluding the discarded data in a second block among the valid data stored in a first block and erase the first block; and a controller to output, in response to a request for reading the discarded data, a response indicating that the data is unable to be read. When all the valid data included in a block are discarded, the discarding unit erases the block.
摘要翻译：根据实施例，半导体存储器件包括半导体存储器芯片，用于存储以页为单位写入和读取的多个数据，并且以包括多个页的块为单位被擦除; 在所述数据被写入所述半导体存储器芯片中，在所述多个数据中的至少一部分有效数据被指定的情况下，丢弃所述丢弃单元; 压缩单元，将存储在第一块中的有效数据中的排除丢弃数据的有效数据写入第二块中，并擦除第一块; 以及控制器，响应于读取丢弃的数据的请求，输出指示数据不能被读取的响应。当包含在块中的所有有效数据被丢弃时，丢弃单元擦除该块。

4. 发明申请

US20100005228A1 DATA CONTROL APPARATUS, STORAGE SYSTEM, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：数据控制设备，存储系统和计算机程序产品
公开(公告)号：US20100005228A1
公开(公告)日：2010-01-07
申请号：US12393654
申请日：2009-02-26
申请人： Kazuhiro FUKUTOMI , Hideaki SATO , Shinichi KANNO , Shigehiro ASANO
发明人： Kazuhiro FUKUTOMI , Hideaki SATO , Shinichi KANNO , Shigehiro ASANO
IPC分类号： G06F12/00 , G06F13/00 , G06F12/02 , G06F11/07
CPC分类号： G06F12/0246 , G06F11/108 , G06F2212/7208 , G06F2212/7211
摘要： A data control apparatus includes a mapping-table managing unit that manages a mapping table that is associated with a corrupted-data recovery function of recording data and error correcting code data as redundant data that is given separately from the data, distributed and stored in units of stripe blocks in the plural nonvolatile semiconductor memory devices, the mapping table containing arrangement information of the data and the error correcting code data; a determining unit that determines whether to differentiate frequencies of writing the data into the semiconductor memory devices; and a changing unit that changes the arrangement information by switching the data stored in units of the stripe blocks managed using the mapping table to differentiate the frequencies of writing the data into the semiconductor memory devices, when the determining unit determines that the frequencies of writing the data into the semiconductor memory devices are to be differentiated.
摘要翻译：数据控制装置包括映射表管理单元，其管理与记录数据的损坏数据恢复功能和纠错码数据相关联的映射表，作为与数据分开地分配并以单元分布和存储的冗余数据所述多个非易失性半导体存储器件中的条形块，所述映射表包含所述数据的排列信息和所述纠错码数据; 确定单元，其确定是否将写入数据的频率区分成半导体存储器件; 以及改变单元，其通过切换存储在使用映射表管理的条带块的单元中的数据来改变排列信息，以将写入数据的频率区分为半导体存储器件，当确定单元确定写入的频率差分数据到半导体存储器件中。

5. 发明申请

US20120221918A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20120221918A1
公开(公告)日：2012-08-30
申请号：US13465624
申请日：2012-05-07
申请人： Shinichi KANNO , Hironori UCHIKAWA
发明人： Shinichi KANNO , Hironori UCHIKAWA
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

6. 发明申请

US20110239083A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110239083A1
公开(公告)日：2011-09-29
申请号：US12889018
申请日：2010-09-23
申请人： Shinichi KANNO
发明人： Shinichi KANNO
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： G06F11/1068 , G06F11/1012 , G06F11/1072 , G06F11/1076 , G11C16/10 , G11C29/52 , G11C2029/0411 , H03M13/1515 , H03M13/29 , H03M13/2906
摘要： A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.
摘要翻译：从原始数据生成CRC码，生成相对于原始数据和CRC码的BCH码，原始数据，CRC码和BCH码被记录在从多个不同平面中选择的页面中的内存芯片通过跨页面的原始数据生成RS码，相对于RS码生成CRC码，生成相对于RS码和CRC码的BCH码，RS码，CRC码， BCH码被记录在与包括原始数据的存储芯片不同的存储芯片中。当读取数据时，通过使用BCH码对原始数据进行纠错，然后计算CRC。如果错误的数量是通过使用RS代码的擦除校正可校正的错误的数量，则通过擦除校正来校正原始数据。如果错误数量超过了RS码的擦除校正能力，则使用RS码进行正常纠错，并进一步利用BCH码进行纠错。

7. 发明申请

US20100161885A1 SEMICONDUCTOR STORAGE DEVICE AND STORAGE CONTROLLING METHOD 审中-公开
标题翻译：半导体存储设备和存储控制方法
公开(公告)号：US20100161885A1
公开(公告)日：2010-06-24
申请号：US12555274
申请日：2009-09-08
申请人： Shinichi KANNO , Shigehiro Asano , Kazuya Kitsunai , Hirokuni Yano , Toshikatsu Hida
发明人： Shinichi KANNO , Shigehiro Asano , Kazuya Kitsunai , Hirokuni Yano , Toshikatsu Hida
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/105 , G11C2216/14
摘要： A semiconductor storage device includes a first storage unit having a plurality of first blocks as data write regions; an instructing unit that issues a write instruction of writing data into the first blocks; a converting unit that converts an external address of input data to a memory position in the first block with reference to a conversion table in which external addresses of the data are associated with the memory positions of the data in the first blocks; and a judging unit that judges whether any of the first blocks store valid data associated with the external address based on the memory positions of the input data, wherein the instructing unit issues the write instruction of writing the data into the first block in which the valid data is not stored, when any of the first blocks does not store the valid data.
摘要翻译：半导体存储装置包括具有作为数据写入区域的多个第一块的第一存储单元; 指示单元，其发出将数据写入到所述第一块中的写入指令; 转换单元，参照其中数据的外部地址与第一块中的数据的存储位置相关联的转换表，将输入数据的外部地址转换为第一块中的存储器位置; 以及判断单元，其基于所述输入数据的存储器位置判断所述第一块是否存储与所述外部地址相关联的有效数据，其中，所述指示单元发出将所述数据写入到所述第一块中的写入指令，当任何第一个块不存储有效数据时，不存储数据。

8. 发明申请

US20120072795A1 SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD 有权
标题翻译：半导体存储器件和控制方法
公开(公告)号：US20120072795A1
公开(公告)日：2012-03-22
申请号：US13038804
申请日：2011-03-02
申请人： Kazumasa YAMAMOTO , Shinichi KANNO , Shigehiro ASANO , Hiroyuki NAGASHIMA
发明人： Kazumasa YAMAMOTO , Shinichi KANNO , Shigehiro ASANO , Hiroyuki NAGASHIMA
IPC分类号： G06F11/267
CPC分类号： G11C16/3418 , G11C16/00 , G11C29/028
摘要： According to one embodiment, a semiconductor memory device includes a plurality of semiconductor memory chips configured to store therein information depending on an amount of accumulated charge; a plurality of parameter storage units that are provided in correspondence with the semiconductor memory chips, each of the plurality of parameter storage units being configured to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and writes the parameters changed into the parameter storage units, respectively.
摘要翻译：根据一个实施例，半导体存储器件包括多个半导体存储器芯片，其被配置为根据累积电荷的量来存储信息; 多个参数存储单元，与所述半导体存储器芯片对应地设置，所述多个参数存储单元中的每一个被配置为在其中存储定义用于将信息写入信息或从其读取信息的信号的电特性的参数对应的一个半导体存储器芯片; 错误校正编码单元，被配置为从存储在半导体存储器芯片中的信息生成能够校正存储在半导体存储器芯片中的不大于预定数量的多个半导体存储器芯片中的信息中的误差的第一校正代码 ; 以及参数处理单元，被配置为分别对应于不大于预定数量的半导体存储器芯片的数量分别改变参数，并将改变的参数分别写入参数存储单元。

9. 发明申请

US20090183052A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20090183052A1
公开(公告)日：2009-07-16
申请号：US12404861
申请日：2009-03-16
申请人： Shinichi KANNO , Hironori Uchikawa
发明人： Shinichi KANNO , Hironori Uchikawa
IPC分类号： H03M13/05 , G06F11/22 , G06F11/07
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
摘要翻译：半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器，包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

10. 发明申请

US20090177944A1 SEMICONDUCTOR MEMORY DEVICE AND ITS CONTROL METHOD 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20090177944A1
公开(公告)日：2009-07-09
申请号：US12400863
申请日：2009-03-10
申请人： Shinichi KANNO
发明人： Shinichi KANNO
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/1068
摘要： A semiconductor memory device includes a temporary storage circuit configured to receive data items and store the data items in rows and columns, a detecting code generator configured to generate first detecting codes used to detect errors in the data items, respectively, a first correcting code generator configured to generate first correcting codes used to correct errors in first data blocks corresponding to the columns, respectively, each of the first data blocks containing data items that are arranged in a corresponding one of the columns, and a second correcting code generator configured to generate second correcting codes used to correct errors in second data blocks corresponding to the rows, respectively, each of the second data blocks containing data items that are arranged in a corresponding one of the rows.
摘要翻译：一种半导体存储器件，包括临时存储电路，被配置为接收数据项并将数据项存储在行和列中;检测码发生器，被配置为分别生成用于检测数据项中的错误的第一检测码;第一校正码发生器被配置为分别产生用于校正与所述列相对应的第一数据块中的错误的第一校正码，每个第一数据块包含布置在对应的一列中的数据项，以及第二校正码生成器，被配置为生成用于分别对应于行的第二数据块中的错误的第二校正码，每个第二数据块包含布置在相应行中的数据项。

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