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    • 3. 发明申请
    • Nonvolatile semiconductor memory including redundant cell for replacing defective cell
    • 非易失性半导体存储器,包括用于替换有缺陷的单元的冗余单元
    • US20060227621A1
    • 2006-10-12
    • US11401418
    • 2006-04-11
    • Takamichi KasaiHideo Kato
    • Takamichi KasaiHideo Kato
    • G11C16/04
    • G11C29/838G11C16/04G11C29/52G11C29/76
    • A nonvolatile semiconductor memory includes a cell array, redundancy array, erase circuit, timer, and controller. The cell array has a plurality of memory cells. The redundancy array has a plurality of redundant cells capable of replacing the memory cell. The erase circuit performs an erase operation on a target cell including the memory cell or the redundant cell. The timer measures the time elapsed from the start of the erase operation performed for the target cell by the erase circuit. The controller stops the erase operation and replaces the target cell with the redundant cell, when detecting that a predetermined time has elapsed from the start of the erase operation by the measurement of the elapsed time by the timer.
    • 非易失性半导体存储器包括单元阵列,冗余阵列,擦除电路,定时器和控制器。 单元阵列具有多个存储单元。 冗余阵列具有能够替换存储单元的多个冗余单元。 擦除电路对包括存储单元或冗余单元的目标单元执行擦除操作。 定时器测量从擦除电路开始对目标单元执行的擦除操作所经过的时间。 当通过定时器测量经过的时间检测到从擦除操作开始经过了预定时间时,控制器停止擦除操作并且用冗余单元替换目标单元。
    • 4. 发明授权
    • Nonvolatile semiconductor memory including redundant cell for replacing defective cell
    • 非易失性半导体存储器,包括用于替换有缺陷的单元的冗余单元
    • US07379331B2
    • 2008-05-27
    • US11401418
    • 2006-04-11
    • Takamichi KasaiHideo Kato
    • Takamichi KasaiHideo Kato
    • G11C11/34
    • G11C29/838G11C16/04G11C29/52G11C29/76
    • A nonvolatile semiconductor memory includes a cell array, redundancy array, erase circuit, timer, and controller. The cell array has a plurality of memory cells. The redundancy array has a plurality of redundant cells capable of replacing the memory cell. The erase circuit performs an erase operation on a target cell including the memory cell or the redundant cell. The timer measures the time elapsed from the start of the erase operation performed for the target cell by the erase circuit. The controller stops the erase operation and replaces the target cell with the redundant cell, when detecting that a predetermined time has elapsed from the start of the erase operation by the measurement of the elapsed time by the timer.
    • 非易失性半导体存储器包括单元阵列,冗余阵列,擦除电路,定时器和控制器。 单元阵列具有多个存储单元。 冗余阵列具有能够替换存储单元的多个冗余单元。 擦除电路对包括存储单元或冗余单元的目标单元执行擦除操作。 定时器测量从擦除电路开始对目标单元执行的擦除操作所经过的时间。 当通过定时器测量经过的时间检测到从擦除操作开始经过了预定时间时,控制器停止擦除操作并用冗余单元替换目标单元。