会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Apparatus and method for cleaning semiconductor substrate
    • 用于清洁半导体衬底的装置和方法
    • US08758521B2
    • 2014-06-24
    • US12845371
    • 2010-07-28
    • Yoshihiro OgawaHajime OnodaHiroshi Kawamoto
    • Yoshihiro OgawaHajime OnodaHiroshi Kawamoto
    • B08B3/04
    • H01L21/67028B08B3/022C11D11/0047H01L21/02057
    • A semiconductor substrate cleaning method includes cleaning a semiconductor substrate formed with a line-and-space pattern, rinsing the substrate, supplying the rinse water to rinse the substrate, and drying the substrate. The rinsing includes supplying deionized water and hydrochloric acid into a mixing section to mix the deionized water and the hydrochloric acid into a mixture, heating the mixture in the mixing section by a heater, detecting a pH value and a temperature of the mixture by a pH sensor and a temperature sensor respectively, adjusting an amount of hydrochloric acid supplied into the mixing section so that the rinse water has a predetermined pH value indicative of acidity, and energizing or de-energizing the heater so that the temperature of the mixture detected by the temperature sensor reaches a predetermined temperature, thereby producing the rinse water which has a temperature of not less than 70° C. and is acidic.
    • 半导体衬底清洁方法包括清洗形成有线间距图案的半导体衬底,漂洗衬底,供应冲洗水以冲洗衬底以及干燥衬底。 漂洗包括将去离子水和盐酸加入到混合部分中以将去离子水和盐酸混合成混合物,通过加热器加热混合部分中的混合物,通过pH检测混合物的pH值和温度 传感器和温度传感器,调节供应到混合部分中的盐酸的量,使得冲洗水具有指示酸度的预定pH值,以及给加热器通电或断电,使得由 温度传感器达到预定温度,从而产生温度不低于70℃并呈酸性的冲洗水。
    • 4. 发明申请
    • Integrated Circuit Design Meethod, Design Assistance Program and Integrated Circuit Design System Using Such Integrated Circuit Design Method
    • 集成电路设计方法,使用这种集成电路设计方法的设计辅助程序和集成电路设计系统
    • US20070266365A1
    • 2007-11-15
    • US10588956
    • 2005-02-10
    • Hiroshi Kawamoto
    • Hiroshi Kawamoto
    • G06F17/50
    • G06F17/5045
    • [PROBLEMS] To provide an integrated circuit design method realized as a photomask/photomaskless fusion method wherein a photomask trial method and a photomaskless trial method are fused with each other so as to obtain both a merit of the photomask trial method allowing production of trial chips without producing photomasks and a merit of the photomaskless trial method allowing use of pattern information for a trial production as pattern information for a mass production trial. To provide a design assistance program and an integrated circuit design system used in such an integrated circuit design method. [SOLVING MEANS] A trial integrated circuit is produced based on pattern information for a trial production, without using a photomask, under a common design circumstance which can be utilized in both a photomaskless step of producing an integrated circuit based on pattern information without using a photomask and a photomask step of producing an integrated circuit based on pattern information with using a photomask, with the pattern information for the trial production complying with both the photomaskless step and the photomask step. A common pattern information is prepared by evaluating the trial integrated circuit and by modifying the pattern information for the trial production in accordance with results of the evaluation, if necessary, without being modified. A photomask for a mass production is produced by carrying out a formal conversion of the common pattern information, if necessary.
    • 提供一种实现为光掩模/无光掩模的融合方法的集成电路设计方法,其中光掩模试验方法和无光掩模试验方法彼此融合,以便获得允许生产试验芯片的光掩模试验方法的优点 不产生光掩模和无光掩模试验方法的优点,允许使用用于试生产的图案信息作为批量生产试验的图案信息。 提供设计辅助程序和在这种集成电路设计方法中使用的集成电路设计系统。 [解决方案]基于在不使用光掩模的情况下,在不使用光掩模的情况下,在可以用于基于图案信息生成集成电路的无光掩模步骤的二次设计环境中生产试用集成电路,而不使用 光掩模和基于使用光掩模的图案信息生成集成电路的光掩模步骤,以及符合无光掩模步骤和光掩模步骤两者的用于试制的图案信息。 通过对试用集成电路进行评估,根据需要进行的评价结果​​修改试生产的图案信息,而不进行修改,来制作通用图案信息。 如果需要,通过对共同图案信息进行正式转换来生产批量生产的光掩模。
    • 9. 发明授权
    • Method for detecting an IC defect using charged particle beam
    • 使用带电粒子束检测IC缺陷的方法
    • US5592100A
    • 1997-01-07
    • US640439
    • 1996-04-30
    • Soichi ShidaHiroshi KawamotoHironobu Niijima
    • Soichi ShidaHiroshi KawamotoHironobu Niijima
    • G01R31/28G01R31/307
    • G01R31/307
    • Test patterns are applied to an IC under test under a test pattern address by which the first fail is caused and under other test pattern addresses. A defect candidate area is moved to the position where a charged particle beam can scan the area and defect candidate wiring portions are specified. A potential data of the specified wiring is acquired for each of the test patterns and stored in a memory. This process is performed by sequentially stepping back the stop test pattern addresses. Then, a potential data of the specified wiring in the specified area is similarly acquired for non-defect IC. The respective potential data of the IC under test and the non-defect IC are compared to locate the mismatch test pattern address and wiring.
    • 在测试模式地址下,测试模式被应用到测试模式地址,由此引起第一个故障,并在其他测试模式地址下。 将缺陷候选区域移动到带电粒子束可以扫描该区域的位置,并且指定缺陷候选布线部分。 针对每个测试图案获取指定布线的潜在数据并存储在存储器中。 该过程通过顺序地退回停止测试模式地址来执行。 然后,对于非缺陷IC,类似地获取指定区域中的指定布线的潜在数据。 将待测IC和非缺陷IC的各自的潜在数据进行比较,以确定不匹配测试模式地址和布线。