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1. 发明授权

US5581585A Phase-locked loop timing recovery circuit 失效
标题翻译：锁相环定时恢复电路
公开(公告)号：US5581585A
公开(公告)日：1996-12-03
申请号：US327184
申请日：1994-10-21
申请人： Hiroshi Takatori , Daniel L. Ray , Kenneth G. Buttle , James W. Everitt
发明人： Hiroshi Takatori , Daniel L. Ray , Kenneth G. Buttle , James W. Everitt
IPC分类号： H04L7/00 , H04L7/02 , H04L7/033 , H04L25/03 , H03H7/30 , H03D3/24
CPC分类号： H04L25/03057 , H04L7/0058 , H04L7/0062 , H04L7/0083
摘要： A timing recovery apparatus for recovering the timing from sparse timing information in multi-level or partial response codes. The timing recovery apparatus includes a switch for sampling an incoming line code signal according to a selectable sample rate, a feed forward equalizer for filtering the sampled signal, a decision feedback equalizer for cancelling intersymbol interference in the filtered signal and for recovering the timing in the sampled signal. The timing recovery circuit creates a phase correction signal in response to a signal received from the feed forward equalizer and thereby control the sample rate of the sample switch so that the signal-to-noise ratio at the node before the decision is maximized. The voltage controlled crystal oscillator may be controlled within a certain frequency range by using a second phase detector which compares the phase of the signal controlling the sampling of the incoming line code with a reference clock.
摘要翻译：一种定时恢复装置，用于从多级或部分响应码中的稀疏定时信息中恢复定时。定时恢复装置包括用于根据可选采样率对输入线路码信号进行采样的开关，用于滤波采样信号的前馈均衡器，用于消除滤波信号中的码间干扰的判决反馈均衡器，以及用于恢复滤波信号中的定时采样信号。定时恢复电路响应于从前馈均衡器接收的信号创建相位校正信号，从而控制采样开关的采样率，使得决定之前的节点处的信噪比最大化。通过使用第二相位检测器将压控晶体振荡器控制在一定频率范围内，该第二相位检测器将控制输入线路码的采样的信号的相位与参考时钟进行比较。

2. 发明授权

US5880645A Analog adaptive equalizer with gain and filter correction 失效
标题翻译：具有增益和滤波器校正的模拟自适应均衡器
公开(公告)号：US5880645A
公开(公告)日：1999-03-09
申请号：US887699
申请日：1997-07-03
申请人： James W. Everitt , Paul J. Hurst , Daniel L. Ray
发明人： James W. Everitt , Paul J. Hurst , Daniel L. Ray
IPC分类号： H04B7/005 , H03H7/30
CPC分类号： H04B7/005
摘要： The analog adaptive equalizer provides convergence of an error signal by decoupling the error canceller, the automatic gain control and the filter to provide truly adaptive error minimization. The invention includes an automatic gain control (AGC) circuit for providing broadband amplification of an input signal to generate an AGC output signal, a filter for receiving the AGC output signal and providing high frequency signal conditioning to generate a filter output signal, an error detection circuit for generating an error signal representing the difference between the filter output signal and an expected output signal and a calculator for receiving the error signal and providing a gain correction signal to the automatic gain circuit to adjust the gain of the automatic gain circuit and a filter control signal to adjust the filter range of the filter, the gain correction signal and the filter control signal being used to cancel the error signal. The calculator further comprises a first in, first out buffer for providing a history of the expected output signal to the calculator.
摘要翻译：模拟自适应均衡器通过解耦误差消除器，自动增益控制和滤波器来提供误差信号的收敛，以提供真正的自适应误差最小化。本发明包括用于提供输入信号的宽带放大以产生AGC输出信号的自动增益控制（AGC）电路，用于接收AGC输出信号并提供高频信号调理以产生滤波器输出信号的滤波器，误差检测用于产生表示滤波器输出信号和预期输出信号之间的差的误差信号的电路和用于接收误差信号的计算器，并向自动增益电路提供增益校正信号，以调整自动增益电路的增益和滤波器控制信号调整滤波器的滤波器范围，增益校正信号和滤波器控制信号用于消除误差信号。计算器还包括用于向计算器提供预期输出信号的历史的第一入口，第一输出缓冲器。

3. 发明授权

US5077529A Wide bandwidth digital phase locked loop with reduced low frequency intrinsic jitter 失效
标题翻译：宽带数字锁相环，降低了低频固有抖动
公开(公告)号：US5077529A
公开(公告)日：1991-12-31
申请号：US382258
申请日：1989-07-19
申请人： Sajol C. Ghoshal , Daniel L. Ray
发明人： Sajol C. Ghoshal , Daniel L. Ray
IPC分类号： H03L7/081 , H03L7/085 , H03L7/099 , H03L7/18 , H04J3/06 , H04L7/033
CPC分类号： H04J3/0626 , H03L7/081 , H03L7/085 , H03L7/0991 , H03L7/18 , H04L7/0331 , H04L7/0337
摘要： A device (16) for reducing the intrinsic low frequency jitter within a Digital Phase lock loop (17). A Digital Phase lock loop high speed clock signal (4) is produced by a multistage oscillator (5), producing a plurality of identical frequency signals, each differing in phase. An adjust signal (18) generated by the Digital Phase lock loop output clock signal (3) causes an adjacent phase angle to be selected as the high speed clock signal (4), thereby reducing the period of the clock signal (4) and, in effect, accelerating the high speed clock signal (4). The current state of the selected phase and the appropriate selection of adjacent phase is monitored by a ten stage shift register (20-29), the presence of a "high bit" within a particular shift register block causing selection of the individual phase (6-15) which serves as the input to that particular shift register stage. An error correction circuit (40) detects the presence of more or less than a single high bit within the shift register stages (20- 29).
摘要翻译：一种用于减少数字锁相环（17）内的固有低频抖动的装置（16）。数字锁相环高速时钟信号（4）由多级振荡器（5）产生，产生多个相位相同的频率信号。由数字锁相环输出时钟信号（3）产生的调整信号（18）使相邻的相位角被选作高速时钟信号（4），从而减小时钟信号（4）的周期，实际上，加速高速时钟信号（4）。所选相位的当前状态和相邻相位的适当选择由十级移位寄存器（20-29）监视，在特定移位寄存器块内存在导致选择单个相位（6）的“高位” -15），其用作该特定移位寄存器级的输入。误差校正电路（40）检测移位寄存器级（20-29）内是否存在多于或少于单个高位。

4. 发明授权

US5008637A Fully integrated charge pump phase locked loop 失效
标题翻译：完全集成的电荷泵锁相环
公开(公告)号：US5008637A
公开(公告)日：1991-04-16
申请号：US437724
申请日：1989-11-15
申请人： Daniel L. Ray
发明人： Daniel L. Ray
IPC分类号： H03L7/089
CPC分类号： H03L7/0893
摘要： A phase locked loop circuit includes a phase detector and an oscillator associated therewith, and a voltage-to-current converter for providing that lag signals sent thereto from the phase detector provide increased signal to the oscillator, and lead signals sent thereto from the phase detector provide decreased signal to the oscillator.
摘要翻译：锁相环电路包括相位检测器和与其相关联的振荡器，以及用于提供从相位检测器发送到其的滞后信号的电压 - 电流转换器向振荡器提供增加的信号，以及从相位检测器发送的引导信号向振荡器提供降低的信号。

5. 发明申请

US20100262029A1 NEEDLE IMPLANTABLE ATRIAL FIBRILLATION MONITOR AND METHODS FOR USE THEREWITH 审中-公开
标题翻译：针型可植入式眼刺激监测仪及其使用方法
公开(公告)号：US20100262029A1
公开(公告)日：2010-10-14
申请号：US12423407
申请日：2009-04-14
申请人： N. Patrick Kelly , Antonio Torrini , Daniel L. Ray
发明人： N. Patrick Kelly , Antonio Torrini , Daniel L. Ray
IPC分类号： A61B5/046
CPC分类号： A61B5/046 , A61B5/7232
摘要： A needle implantable atrial fibrillation monitor includes a plurality of terminals that generate a terminal voltage when the needle implantable atrial fibrillation monitor is implanted in a patient's body. An analog processing circuit generates a monitoring signal based on the terminal voltage. An analog to digital converter converts the monitoring signal to monitoring data. A processor analyzes the monitoring data, generates events and compresses the event data and that generates compressed data in response thereto. A memory stores the compressed data. An RF interface transmits the compressed data to a base station via RF signaling when the needle implantable atrial fibrillation monitor is implanted in the patient's body.
摘要翻译：针可植入心房颤动监测器包括当针可植入心房颤动监测器植入患者体内时产生终端电压的多个端子。模拟处理电路根据端子电压产生监视信号。模数转换器将监控信号转换为监控数据。处理器分析监视数据，生成事件并压缩事件数据，并响应于此生成压缩数据。存储器存储压缩数据。当针可植入心房颤动监测器植入患者体内时，RF接口通过RF信号将压缩数据发送到基站。

6. 发明授权

US5267269A System and method employing predetermined waveforms for transmit equalization 失效
标题翻译：采用预定波形进行发送均衡的系统和方法
公开(公告)号：US5267269A
公开(公告)日：1993-11-30
申请号：US754604
申请日：1991-09-04
申请人： Cheng-chung Shih , Haim Shafir , Stefan M. Wurster , Cecil Aswell , Daniel L. Ray , Joseph E. Heideman
发明人： Cheng-chung Shih , Haim Shafir , Stefan M. Wurster , Cecil Aswell , Daniel L. Ray , Joseph E. Heideman
IPC分类号： H04L25/03 , H04L25/08 , H04L25/49
CPC分类号： H04L25/03866 , H04L25/08 , H04L25/4904
摘要： A data communication system employing predetermined equalized waveforms for transmit equalization is disclosed. Serial NRZ data is received from a network controller and utilized to select from memory its equivalent as predistorted and filtered Manchester encoded data. Predetermined waveforms in memory are representative of the analog waveform produced when predistorted digital Manchester encoded data is passed through a high order transmit filter. Data from memory drives a digital to analog converter (DAC) to reconstruct the waveforms into analog form. A line driver having an integrated single pole low pass filter impresses the equalized waveform on to the transmission line.
摘要翻译：公开了一种采用预定均衡波形进行发送均衡的数据通信系统。从网络控制器接收串行NRZ数据，并用于从存储器中选择其等同物作为预失真和滤波的曼彻斯特编码数据。存储器中的预定波形表示当预失真数字曼彻斯特编码数据通过高阶发射滤波器时产生的模拟波形。来自存储器的数据驱动数模转换器（DAC），将波形重建为模拟形式。具有集成单极低通滤波器的线路驱动器将均衡波形印在传输线上。

7. 发明授权

US5204880A Differential line driver employing predistortion 失效
标题翻译：差分线路驱动器采用预失真
公开(公告)号：US5204880A
公开(公告)日：1993-04-20
申请号：US690087
申请日：1991-04-23
申请人： Stefan M. Wurster , Daniel L. Ray
发明人： Stefan M. Wurster , Daniel L. Ray
IPC分类号： H04B1/62
CPC分类号： H04L25/0266 , H04B1/62
摘要： A two terminal line driver employing predistortion is disclosed, for driving data over a lossy transmission line such as a twisted pair cable at speeds on upwards of 10 Mbit/s. The driver is designed for voltage output operation wherein fullstep and halfstep information is actively encoded into a voltage level provided for at the output terminals. The driver provides a fullstep voltage spanning the supply rails and a halfstep voltage having a selectable controlled amplitude of a predetermined value. Fat bits resulting from the biphase encoding format are predistorted by dropping the amplitude to a predetermined value, equalizing the relative power content.
摘要翻译：公开了一种采用预失真的两端线路驱动器，用于以超过10Mbit / s的速度通过有线传输线（例如双绞线电缆）驱动数据。驱动器被设计用于电压输出操作，其中全步和半步信息被主动编码为在输出端提供的电压电平。驱动器提供横跨电源轨的全步电压和具有预定值的可选择的受控幅度的半步电压。由双相编码格式产生的脂肪位是通过将振幅降到预定值来预失真的，使相对功率内容相等。

8. 发明授权

US5257286A High frequency receive equalizer 失效
标题翻译：高频接收均衡器
公开(公告)号：US5257286A
公开(公告)日：1993-10-26
申请号：US612321
申请日：1990-11-13
申请人： Daniel L. Ray
发明人： Daniel L. Ray
IPC分类号： H04B3/14 , H04L25/03
CPC分类号： H04L25/03019 , H04B3/145
摘要： A high frequency receive equalizer for baseband data recovery is disclosed utilizing a frequency selective equalization filter to restore dispersed pulses into a recoverable form. The frequency selective equalization filter has a plurality of independently adjustable stages. Received pulses are passed through an equalization filter whose output is monitored by equalizer feedback control means. The feedback control means adjusts the amount of equalization applied until the amplitude of the equalized pulses reaches a predetermined level.
摘要翻译：公开了一种用于基带数据恢复的高频接收均衡器，其利用频率选择均衡滤波器将分散的脉冲恢复成可恢复的形式。频率选择均衡滤波器具有多个可独立调节的级。接收脉冲通过均衡滤波器，其均衡器反馈控制装置监视其输出。反馈控制装置调整所施加的均衡量，直到均衡脉冲的幅度达到预定水平。

9. 发明授权

US5028888A Multistage current-controlled oscillator 失效
标题翻译：多级电流控制振荡器
公开(公告)号：US5028888A
公开(公告)日：1991-07-02
申请号：US436848
申请日：1989-11-15
申请人： Daniel L. Ray
发明人： Daniel L. Ray
IPC分类号： H03K3/03 , H03K3/354
CPC分类号： H03K3/0315 , H03K3/354
摘要： A current-controlled oscillator includes a plurality of switches for generating a time delay signal, each switch including an MOS transistor operatively coupled to the next gate by means including a capacitor, the final MOS transistor being connected to the initial MOS transistor by a feedback conductor also operatively connected with a capacitor. The frequency of the oscillator is varied by varying current injected into the oscillator.
摘要翻译：电流控制振荡器包括用于产生时间延迟信号的多个开关，每个开关包括通过包括电容器的装置可操作地耦合到下一个栅极的MOS晶体管，最终MOS晶体管通过反馈导体连接到初始MOS晶体管也可操作地与电容器连接。振荡器的频率通过改变注入振荡器的电流来改变。

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