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    • 5. 发明授权
    • Sample-and-hold circuit
    • 采样保持电路
    • US5467035A
    • 1995-11-14
    • US315716
    • 1994-09-30
    • Susumu OhiHiroshi Shiba
    • Susumu OhiHiroshi Shiba
    • G11C27/02H03K17/66H03K5/00
    • H03K17/667G11C27/026
    • An input terminal is connected to bases of first and second transistors. Collectors of the first and fourth transistors are connected to a power-source terminal. Collectors of the second and third transistors are grounded. A base of the third transistor is connected to an emitter of the first transistor. A base of the fourth transistor is connected to an emitter of the second transistor. One terminal of the capacitor is grounded and the other terminal thereof is connected to emitters of the third and fourth transistors and an input of an output buffer whose output is connected to an output terminal. A collector of a fifth transistor is connected to the power-source terminal and a base thereof is connected to the output terminal. A collector of a sixth transistor is grounded and a base thereof is connected to the output terminal. A first constant-current source is connected to an emitter of the fifth transistor and a base of the fourth transistor. A second constant-current source is connected to an emitter of the sixth transistor and the base of the third transistor. A third constant-current source is connected to the emitter of the first transistor and turned on at a sampling time. A fourth constant-current source is connected to the emitter of the second transistor and turned on at the sampling time.
    • 输入端子连接到第一和第二晶体管的基极。 第一和第四晶体管的集电极连接到电源端子。 第二和第三晶体管的集电极接地。 第三晶体管的基极连接到第一晶体管的发射极。 第四晶体管的基极连接到第二晶体管的发射极。 电容器的一个端子接地,另一个端子连接到第三和第四晶体管的发射极,输出端连接到输出端子的输出缓冲器的输入端。 第五晶体管的集电极连接到电源端子,其基极连接到输出端子。 第六晶体管的集电极接地,其基极连接到输出端子。 第一恒流源连接到第五晶体管的发射极和第四晶体管的基极。 第二恒流源连接到第六晶体管的发射极和第三晶体管的基极。 第三恒流源连接到第一晶体管的发射极,并在采样时间导通。 第四恒流源连接到第二晶体管的发射极,并在采样时间导通。