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    • 2. 发明授权
    • Frequency discriminating circuit
    • 鉴频电路
    • US3997797A
    • 1976-12-14
    • US645873
    • 1975-12-31
    • Hiroshi SaharaYutaka TanakaToshinobu Isobe
    • Hiroshi SaharaYutaka TanakaToshinobu Isobe
    • H03D3/08H03D3/10H04N9/64H04N11/18H03D3/26
    • H03D3/08H04N11/186H04N5/44
    • A frequency discriminating circuit having a double tuned circuit with a transformer, which has a first and second resonant circuits. The first resonant circuit is composed of a capacitor, a primary winding of the transformer and a first variable inductance element and the second resonant circuit is composed of a capacitor, a secondary winding of the transformer and second and third variable inductance elements, wherein the quality factor Q of the second resonant circuit is much larger than that Q of the first resonant circuit. The center frequency of the frequency-response characteristic (so-called S characteristic) of the discriminating circuit can be adjusted by adjusting the second and third variable inductance elements and the linearity of the frequency response characteristic of the discriminating circuit can be adjusted by adjusting the first variable inductance element.
    • 一种具有带有变压器的双调谐电路的频率判别电路,其具有第一和第二谐振电路。 第一谐振电路由电容器,变压器的初级绕组和第一可变电感元件组成,第二谐振电路由电容器,变压器的次级绕组和第二和第三可变电感元件组成,其中质量 第二谐振电路的因子Q比第一谐振电路的Q大得多。 鉴别电路的频率响应特性(所谓的S特性)的中心频率可以通过调节第二和第三可变电感元件来调节,并且可以通过调节判别电路的频率响应特性的线性来调节 第一可变电感元件。
    • 4. 发明授权
    • Flicker preventing circuit
    • 防闪烁电路
    • US4412251A
    • 1983-10-25
    • US298106
    • 1981-08-31
    • Yutaka TanakaToshinobu Isobe
    • Yutaka TanakaToshinobu Isobe
    • H04N5/21G09G1/14H04N5/14
    • H04N7/0132G09G1/146Y10S348/91
    • A flicker preventing circuit for a television receiver is disclosed which includes a first delay line for delaying an input video signal by one horizontal sweep period and producing a first delayed signal, a second delay line for delaying the input video signal by two horizontal periods and producing a second delayed signal, a switching circuit for selecting either the input video signal or the second delayed signal, the switching circuit being switched alternately according to which of the even and odd interlaced fields, respectively, is being displayed, an adder for adding the output signal from the switching circuit and the first delayed signal each other, and a level changing circuit for changing the level of either the input video signal or the second delayed signal relative to the level of the first delayed signal.
    • 公开了一种电视接收机防闪烁电路,它包括一个用于将输入视频信号延迟一个水平扫描周期并产生第一延迟信号的第一延迟线,用于将输入视频信号延迟两个水平周期的第二延迟线,并产生 第二延迟信号,用于选择输入视频信号或第二延迟信号的切换电路,切换电路根据正在显示的偶数和奇数交错场中的哪一个被交替地切换;加法器,用于将输出 来自开关电路的信号和第一延迟信号;以及电平改变电路,用于相对于第一延迟信号的电平改变输入视频信号或第二延迟信号的电平。
    • 6. 发明授权
    • Video signal reproducing apparatus with electron beam scanning velocity
modulation
    • 具有电子束扫描速度调制的视频信号再生装置
    • US4183064A
    • 1980-01-08
    • US852790
    • 1977-11-18
    • Hiroshi SaharaYutaka Tanaka
    • Hiroshi SaharaYutaka Tanaka
    • H04N5/208H04N3/32
    • H04N3/32
    • In a video signal reproducing apparatus having a cathode ray tube in which at least one electron beam is made to scan a screen in line-scanning and vertical directions while the intensity of the beam is modulated to establish the brightness of a video picture to be displayed on the screen, and in which bright picture portions are represented by respective high level portions of a video signal; a waveshaping circuit receives the video signal and acts thereon to provide a compensated video signal in which the width of each high level portion between the respective rising and falling edges is increased, the compensated video signal is employed to control the intensity of the electron beam, and the rising and falling edges of each high level portion of the compensated video signal are detected, as by a differentiating circuit or a delay line circuit, to provide respective output signals by which the scanning velocity of the beam in the line-scanning direction is modulated. The waveshaping circuit for providing the compensated video signal may be constituted by a delay line and an OR circuit having inputs to which the original video signal and the delayed video signal are applied, or by a differentiator receiving the original video signal and having its output applied to a polarity equalizer.
    • 在具有阴极射线管的视频信号再现装置中,其中使至少一个电子束在线扫描和垂直方向上扫描屏幕,同时调节光束的强度以建立要显示的视频图像的亮度 并且其中亮视图部分由视频信号的相应高级部分表示; 波形成形电路接收视频信号并作用在其上以提供补偿的视频信号,其中相应的上升沿和下降沿之间的每个高电平部分的宽度增加,补偿的视频信号用于控制电子束的强度, 并且通过微分电路或延迟线电路检测补偿视频信号的每个高电平部分的上升沿和下降沿,以提供相应的输出信号,通过该信号,沿扫描方向的光束的扫描速度为 调制。 用于提供经补偿的视频信号的波形成形电路可以由具有输入的延迟线和OR电路构成,OR电路具有应用原始视频信号和延迟的视频信号的输入,或由接收原始视频信号的微分器并且其输出被应用 到极性均衡器。
    • 8. 发明申请
    • GLOW PLUG CONTROL DRIVE METHOD AND GLOW PLUG DRIVE CONTROL SYSTEM
    • GLOW插头控制驱动方法和GLOW PLUG驱动控制系统
    • US20130255615A1
    • 2013-10-03
    • US13993165
    • 2011-12-06
    • Yoshito HujishiroYutaka TanakaTomohiro Nakamura
    • Yoshito HujishiroYutaka TanakaTomohiro Nakamura
    • F02P23/00
    • F02P23/00F02D2041/2027F02P19/02F02P19/022F02P19/023F02P19/026F23Q7/001
    • To suppress current fluctuations upon commencement of driving and prolong lifespan by reducing electric stress caused by current fluctuations.A glow plug 1, a glow switch 2, and a stabilizing coil 3 are series-connected, and upon commencement of the driving of the glow plug 1, a repetition frequency of PWM signals that control the opening and closing of the glow switch 2 is made into a higher frequency than a repetition frequency in a normal drive state and the opening and closing of the glow switch 2 is controlled (S104), and when a predetermined drive shift condition has been met (S106), the repetition frequency of the PWM signals is returned to the frequency during normal driving and the opening and closing of the glow switch 2 is controlled (S108), whereby the current upon commencement of driving is smoothed and the occurrence of an instantaneous large current is suppressed.
    • 为了抑制驱动开始时的电流波动,通过减少由电流波动引起的电应力来延长寿命。 电热塞1,辉光开关2和稳定线圈3是串联的,并且在电热塞1的驱动开始时,控制辉光开关2的打开和关闭的PWM信号的重复频率是 在正常驱动状态下被制成比重复频率高的频率,并且控制辉光开关2的打开和关闭(S104),并且当满足预定的驱动移位条件(S106)时,PWM的重复频率 信号在正常驱动期间返回到频率,并且控制辉光开关2的打开和关闭(S108),从而驱动开始时的电流平滑,并且抑制了瞬时大电流的发生。
    • 9. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08159852B2
    • 2012-04-17
    • US12398839
    • 2009-03-05
    • Toshiyuki KouchiYutaka Tanaka
    • Toshiyuki KouchiYutaka Tanaka
    • G11C5/02
    • G11C8/16G11C11/412
    • A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.
    • 半导体存储器件包括第一和第二驱动晶体管; 第一和第二负载晶体管; 以及第一和第二传输晶体管。 它们各自的漏极扩散层彼此隔离。 半导体存储器件还包括其中布置第一和第二驱动晶体管,第一和第二负载晶体管以及第一和第二传输晶体管的位单元; 用于连接第一驱动晶体管,第一负载晶体管和第一透射晶体管的各自的漏极的第一布线; 以及用于连接其第二驱动晶体管,第二负载晶体管和第二传输晶体管的各自的漏极的第二布线。
    • 10. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20090268499A1
    • 2009-10-29
    • US12398839
    • 2009-03-05
    • Toshiyuki KouchiYutaka Tanaka
    • Toshiyuki KouchiYutaka Tanaka
    • G11C5/02G11C5/06G11C8/16
    • G11C8/16G11C11/412
    • A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.
    • 半导体存储器件包括第一和第二驱动晶体管; 第一和第二负载晶体管; 以及第一和第二传输晶体管。 它们各自的漏极扩散层彼此隔离。 半导体存储器件还包括其中布置第一和第二驱动晶体管,第一和第二负载晶体管以及第一和第二传输晶体管的位单元; 用于连接第一驱动晶体管,第一负载晶体管和第一透射晶体管的各自的漏极的第一布线; 以及用于连接其第二驱动晶体管,第二负载晶体管和第二传输晶体管的各自的漏极的第二布线。