专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5218313A Frequency synthesizer for implementing generator of highly pure signals and circuit devices, such as VCO, PLL and SG used therein 失效
标题翻译：用于实现高纯度信号和电路设备的发生器的频率合成器，例如其中使用的VCO，PLL和SG
公开(公告)号：US5218313A
公开(公告)日：1993-06-08
申请号：US767012
申请日：1991-09-27
申请人： Hiroshi Saeki , Hatsuo Motoyama
发明人： Hiroshi Saeki , Hatsuo Motoyama
IPC分类号： H03B1/00 , H03B5/12 , H03B19/20 , H03B21/01 , H03L7/093 , H03L7/113
CPC分类号： H03L7/113 , H03B19/20 , H03B21/01 , H03B5/1203 , H03B5/1231 , H03B5/1243 , H03B5/1293 , H03L7/093 , H03B2200/0034 , H03B2200/0042 , H03B2201/0208 , H03B2201/033
摘要： To output desired high purity signals, a frequency synthesizer was made to synthesize reference signals from a first and second signal generators in the same frequency band as a desired frequency band. Thereby, the resolution of the frequency synthesizer becomes twice the step .DELTA.F. Also, the frequency synthesizer can interpolate the step size of the first signal generator with half the number of steps. While, heretofore, the 100 MHz step size was interpolated with Fq=0, 10, 20, 30, 40 and 50 MHz, Fq=0, 20, 40 MHz interpolation is made possible. This permits the synthesis of 580 MHz to 1280 MHz. In this case, however, the minimum difference between the sum and difference frequencies from the first and second signal generators is 40 MHz and the lowest frequency is 20 MHz. Thus, depending on mixer isolation, the spurious measures become difficult. The frequency synthesizer of the present invention pays attention to the fact that 20 MHz step signals can be synthesized at frequencies which are integral multiples of Fq (multiples of 0 and 5 are excluded). When two-fold Fq is used, the minimum difference between the sum and difference frequencies output from a mixer is 80 MHz and the lowest used frequency is 40 MHz. The spurious measures by a PLL circuit becomes easy. A frequency detector forces the free-running frequency of a VCO included the PLL circuit. Control Data P and Q to the first and second signal generators are supplied from a control section based on data Fi set by a frequency setting section.
摘要翻译：为了输出期望的高纯度信号，频率合成器在与所需频带相同的频带中合成来自第一和第二信号发生器的参考信号。因此，频率合成器的分辨率变为DELTA F的两倍。此外，频率合成器可以用步数的一半内插第一信号发生器的步长。然而，迄今为止，使用Fq = 0,10,20,30,40和50MHz对100MHz步长进行内插，可以实现Fq = 0,20,40MHz内插。这允许合成580MHz至1280MHz。然而，在这种情况下，来自第一和第二信号发生器的和频和差频之间的最小差为40MHz，最低频率为20MHz。因此，根据混频器隔离，杂散措施变得困难。本发明的频率合成器注意到可以以Fq的整数倍的频率合成20MHz的步进信号（排除0和5的倍数）的事实。当使用双重Fq时，从混频器输出的和频和差频之间的最小差为80 MHz，最低使用频率为40 MHz。 PLL电路的杂散措施变得容易。频率检测器强制包括PLL电路的VCO的自由运行频率。基于由频率设定部设定的数据Fi，从控制部分向第一和第二信号发生器提供控制数据P和Q。

2. 发明授权

US5254955A Advanced phase locked loop circuit 失效
标题翻译：高级锁相环电路
公开(公告)号：US5254955A
公开(公告)日：1993-10-19
申请号：US727840
申请日：1991-07-09
申请人： Hiroshi Saeki , Hatsuo Motoyama
发明人： Hiroshi Saeki , Hatsuo Motoyama
IPC分类号： H03B1/00 , H03B5/12 , H03B19/20 , H03B21/01 , H03L7/093 , H03L7/113 , H03K5/13 , H03K5/22
CPC分类号： H03L7/113 , H03B19/20 , H03B21/01 , H03B5/1203 , H03B5/1231 , H03B5/1243 , H03B5/1293 , H03L7/093 , H03B2200/0034 , H03B2200/0042 , H03B2201/0208 , H03B2201/033
摘要： A PLL circuit comprises a voltage controlled oscillator responsive to a control signal to output an output signal having a variable oscillation frequency; a phase detector for making a phase comparison between the output signal from the voltage controlled oscillator and a reference signal, and for outputting an output error signal; an integrator for integrating the output error signal from the phase detector to extract a direct current variable component contained in the output error signal, the integrator having a first cutoff frequency; and a loop filter for feeding the direct current variable component from the integrator to the voltage controlled oscillator as the control signal to synchronize the output signal from the voltage controlled oscillator with the reference signal. An alternate current coupling circuit is provided for adding only an alternate current component contained in the output error signal from the phase detector to the control signal for feeding to the voltage controlled oscillator; and a compensating circuit is inserted in an alternate current signal path of the alternate current coupling circuit. The compensating circuit is inserted in an alternate current signal path of the alternate current coupling circuit. The compensating circuit has a second cutoff frequency exceeding the first cutoff frequency of the integrator, so that a wide band characteristic is obtained, and SSB phase noise suppression is improved.
摘要翻译： PLL电路包括响应于控制信号的压控振荡器以输出具有可变振荡频率的输出信号; 相位检测器，用于在来自压控振荡器的输出信号和参考信号之间进行相位比较，并输出输出误差信号; 积分器，用于积分来自相位检测器的输出误差信号，以提取包含在输出误差信号中的直流可变分量，积分器具有第一截止频率; 以及环路滤波器，用于将来自积分器的直流可变分量馈送到压控振荡器作为控制信号，以将来自压控振荡器的输出信号与参考信号同步。提供交流电流耦合电路，用于仅将来自相位检测器的输出误差信号中包含的交流电流分量与用于馈送到压控振荡器的控制信号相加; 并且补偿电路被插入到交流电流耦合电路的交流信号路径中。补偿电路插入交流电流耦合电路的交流电流信号路径。补偿电路具有超过积分器的第一截止频率的第二截止频率，从而获得宽带特性，并提高SSB相位噪声抑制。

3. 发明授权

US5160902A Voltage controlled oscillator with controlled capacitance ratio in positive feedback loop to broaden bandwidth 失效
标题翻译：电压控制振荡器在正反馈回路中具有受控电容比，以扩大带宽
公开(公告)号：US5160902A
公开(公告)日：1992-11-03
申请号：US727839
申请日：1991-07-09
申请人： Hiroshi Saeki , Hatsuo Motoyama
发明人： Hiroshi Saeki , Hatsuo Motoyama
IPC分类号： H03B1/00 , H03B5/12 , H03B19/16 , H03B19/20 , H03B21/01 , H03L7/093 , H03L7/113
CPC分类号： H03B19/16 , H03B19/20 , H03B21/01 , H03B5/1203 , H03B5/1231 , H03B5/1243 , H03B5/1262 , H03B5/1293 , H03L7/093 , H03L7/113 , H03B2200/0034 , H03B2200/0042 , H03B2201/0208 , H03B2201/0216 , H03B2201/033
摘要： A voltage controlled oscillator comprises a resonant circuit having at least a coil and a first variable capacitance diode, and resonating within predetermined variable frequency ranges; and an active circuit having an input, an output, and an active element connected between the input and the output, the input being connected to the resonant circuit in order to receive a resonant output therefrom. A variable capacitance ratio circuit, having a second variable capacitance diode and at least one capacitor, is connected in a positive feedback manner, between the input and the output of said active circuit means in order to oscillate the active element of the active circuit at a resonant frequency of the resonant circuit, between the input and the output of the active circuit. A variable controller is provided for changing a resonant frequency of the resonant circuit, to thereby apply a control voltage to the first and second variable capacitance diodes and to control a capacitance ratio between the at least one capacitor and the second variable capacitance diode in the variable capacitance ratio circuit, so that an oscillator frequency of the active element can be changed substantially linearly over a wide bandwidth of no less than one octachord in accordance with a variation in the control voltage, to thereby retain the amount of positive feedback at a predetermined level against the oscillator frequency of the active circuit.
摘要翻译：压控振荡器包括具有至少线圈和第一可变电容二极管并在预定可变频率范围内谐振的谐振电路; 以及有源电路，其具有连接在输入和输出之间的输入，输出和有源元件，输入端连接到谐振电路，以便从其接收谐振输出。具有第二可变电容二极管和至少一个电容器的可变电容比电路以正反馈的方式连接在所述有源电路装置的输入和输出之间，以便将有源电路的有源元件在谐振电路的谐振频率，有源电路的输入和输出之间。提供了一种可变控制器，用于改变谐振电路的谐振频率，从而对第一和第二可变电容二极管施加控制电压，并且控制变量中的至少一个电容器和第二可变电容二极管之间的电容比电容比电路，使得有源元件的振荡器频率可以根据控制电压的变化在宽度不小于一个八角形的宽带宽上基本上线性地改变，从而将正反馈量保持在预定水平针对有源电路的振荡器频率。

4. 发明授权

US5122763A Frequency snythesizer for implementing generator of highly pure signals and circuit devices, such as VCQ, BLL and SG, used therein 失效
标题翻译：用于实施高纯度信号和电路设备的发生器的频率SNYTHESIZER，如VCQ，BLL和SG，使用它们
公开(公告)号：US5122763A
公开(公告)日：1992-06-16
申请号：US570048
申请日：1990-08-20
申请人： Hiroshi Saeki , Hatsuo Motoyama
发明人： Hiroshi Saeki , Hatsuo Motoyama
IPC分类号： H03B1/00 , H03B5/12 , H03B19/16 , H03B19/20 , H03B21/01 , H03L7/093 , H03L7/113
CPC分类号： H03B19/16 , H03B19/20 , H03B21/01 , H03B5/1203 , H03B5/1231 , H03B5/1243 , H03B5/1262 , H03B5/1293 , H03L7/093 , H03L7/113 , H03B2200/0034 , H03B2200/0042 , H03B2201/0208 , H03B2201/0216 , H03B2201/033
摘要： A frequency synthesizer includes a control section; a first signal generator responsive to the control section for selectively outputting one of frequency signals whose frequencies are represented by Fp=a.times..vertline.P.vertline..times..DELTA.F (where the coefficient a is a positive odd number and the coefficient p is an integer); and a second signal generator responsive to the control section for selectively outputting one of frequencies whose frequencies are represented by Fq=b.times..vertline.Q.vertline..times..DELTA.F (where the coefficient b is a positive integer exclusive of integral multiples of prime factors into which a is resolved, and the coefficient Q is an integer and satisfying the expression: .vertline.Q.vertline..ltoreq.(a-1)/2. A mixer mixes a frequency signal Fp from the first signal generator and a frequency signal Fq from the second signal generator; and a frequency selecting circuit selects either of frequency signals .vertline.FP-Fq.vertline. or Fp+Fq output from the mixer. The control section determines the values of P and Q satisfying the following expresion P=T+(S-b.times.Q)/a on the basis of a desired frequency signal Fi=m.times..DELTA.F, a coefficient m=0, 1, 2, ..n set in predetermined frequency .DELTA.F; and quotient T and remainder s of m/a to cause each of the first and second signal generators to output a predetermined frequency and the frequency selecting circuit to select one of the frequency signals .vertline.Fp-Fq.vertline. and Fp+Fq that corresponds to the frequency signal Fi.

5. 发明授权

US5808493A Rational frequency division device and frequency synthesizer using the same 失效
标题翻译：合理的分频装置和频率合成器使用相同的
公开(公告)号：US5808493A
公开(公告)日：1998-09-15
申请号：US809022
申请日：1997-03-12
申请人： Norihiro Akiyama , Hirokazu Yanagawa , Hatsuo Motoyama
发明人： Norihiro Akiyama , Hirokazu Yanagawa , Hatsuo Motoyama
IPC分类号： G06F7/68 , H03L7/197 , H03L7/06
CPC分类号： G06F7/68 , H03L7/1976
摘要： A rational frequency division device eliminates spurious components by a simple arrangement and can set a broad frequency modulation range. A frequency synthesizer using the rational frequency division device includes an arithmetic circuit, which outputs the frequency division ratio to a frequency divider in a PLL circuit constituted by a variable frequency oscillator 4, a frequency divider 6, and a phase detector 2. The arithmetic circuit includes a plurality of series-connected cumulative adders 22 which include a first cumulative adder that receives a rational number defined by an integer value and a decimal value, an integer value extraction circuit 23 for extracting an integer value from the output value of the cumulative adder of the final stage, and a delay circuit 24 for outputting the integer value extracted by the integer value extraction circuit to the frequency divider as the frequency division ratio, and outputting the integer value to the respective cumulative adders as a feedback value. Each cumulative adder adds a value calculated by itself in the previous clock period to the input rational number or the output value from the cumulative adder of the previous stage, and subtracts the feedback value from the delay circuit therefrom, thus outputting the calculated value.
摘要翻译： PCT No.PCT / JP96 / 02143 Sec。 371日期1997年3月12日 102（e）1997年3月12日PCT PCT 1996年7月30日PCT公布。出版物WO97 / 06600 日期1997年2月20日合理的分频装置通过简单的布置消除杂散分量，并可以设置宽的频率调制范围。使用有理分频装置的频率合成器包括：运算电路，其将分频比输出到由可变频率振荡器4，分频器6和相位检测器2构成的PLL电路中的分频器。运算电路包括多个串联连接的累积加法器22，其包括接收由整数值和十进制值定义的有理数的第一累积加法器，用于从累积加法器的输出值中提取整数值的整数值提取电路23 以及用于将由整数值提取电路提取的整数值输出到分频器的延迟电路24作为分频比，并将整数值作为反馈值输出到各累积加法器。每个累积加法器将在前一时钟周期中自己计算的值与前一级的累积加法器的输入有理数或输出值相加，并从其延迟电路中减去反馈值，从而输出计算值。

6. 发明授权

US4659999A Direct frequency synthesizer which is step-wise variable and has phase continuity and phase reproducibility when switching frequencies 失效
标题翻译：直接频率合成器，它是逐步可变的，并具有相位连续性和相位重现性，当开关频率
公开(公告)号：US4659999A
公开(公告)日：1987-04-21
申请号：US664401
申请日：1984-10-24
申请人： Hatsuo Motoyama , Tetsuo Igawa
发明人： Hatsuo Motoyama , Tetsuo Igawa
IPC分类号： H03L7/16 , H03B1/00 , H03B21/02 , H03B23/00 , H03C3/09 , H03L7/22 , H04L27/12 , H04L27/20 , H03L7/00
CPC分类号： H04L27/2014 , H03B21/02 , H03B23/00 , H03L7/22 , H03C3/0908
摘要： In a signal generator based on Direct Frequency Synthesis, a first reference frequency generator generates a signal of a reference frequency. A plurality of second reference frequency generators, respectively, generates K signals with different frequencies Asin(.omega..sub.1 t+.psi.), Asin(.omega..sub.2 t+.psi.) . . . Asin(.omega..sub.K t+.psi.), which are in phase at time point (t=0), in response to the output signal of the first reference frequency generator. A switching circuit selectively switches the output signals from the plurality of said second reference frequency generators. A timing pulse generator generates timing pulses to operate said switching circuit at time T as given by .vertline..omega..sub.i+1 T-.omega..sub.i T.vertline.=2l.pi. (l:integer) where i=1, 2 . . . K-1.
摘要翻译：在基于直接频率合成的信号发生器中，第一参考频率发生器产生参考频率的信号。多个第二参考频率发生器分别产生具有不同频率Asin（ω1t + psi），Asin（ω2t + psi）的K个信号。。。响应于第一参考频率发生器的输出信号，在时间点（t = 0）同相的Asin（ω= Kt + psi）。开关电路有选择地切换来自多个所述第二参考频率发生器的输出信号。定时脉冲发生器产生定时脉冲，以在时间T处操作所述开关电路，如由|ωi + 1T-ωi = 2l pi（l：integer）给出，其中i = 1,2。。。 K-1。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式