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1. 发明授权

US5825817A Radio wave measuring apparatus for digital communication system 失效
标题翻译：数字通信系统无线电波测量仪
公开(公告)号：US5825817A
公开(公告)日：1998-10-20
申请号：US504736
申请日：1995-07-19
申请人： Takanori Tanaka , Yasuhiko Shimura , Hirokazu Yanagawa
发明人： Takanori Tanaka , Yasuhiko Shimura , Hirokazu Yanagawa
IPC分类号： H04L1/20 , H04J3/00
CPC分类号： H04L1/20
摘要： In one aspect of this invention, a receiver sequentially demodulates sequentially received burst signals into original digital data signals. A data extraction unit extracts base station information from the digital data signals sequentially demodulated by the receiver. A level detector detects the signal levels of received signals containing the burst signals sequentially received by the receiver. A control unit causes a display unit to display the signal levels detected by the level detector in accordance with elapse of the reception time, and display the base station information extracted by the data extraction unit. In another aspect of this invention, a determination unit quantitatively determines errors of the burst signals from the digital data signals sequentially demodulated by the receiver, and outputs the determination results concerning the validity of the digital data contained in the burst signals. The data processing unit causes the display unit to display the measurement levels and the determination results concerning the validity of the data for designated base stations.
摘要翻译：在本发明的一个方面，接收机顺序地将顺序地接收的脉冲信号解调成原始的数字数据信号。数据提取单元从由接收机顺序解调的数字数据信号中提取基站信息。电平检测器检测包含由接收机顺序接收的突发信号的接收信号的信号电平。控制单元使显示单元根据接收时间的经过显示由电平检测器检测到的信号电平，并显示由数据提取单元提取的基站信息。在本发明的另一方面，确定单元定量地确定由接收机顺序解调的数字数据信号中的突发信号的误差，并且输出关于包含在突发信号中的数字数据的有效性的确定结果。数据处理单元使显示单元显示关于指定基站的数据的有效性的测量水平和确定结果。

2. 发明授权

US5808493A Rational frequency division device and frequency synthesizer using the same 失效
标题翻译：合理的分频装置和频率合成器使用相同的
公开(公告)号：US5808493A
公开(公告)日：1998-09-15
申请号：US809022
申请日：1997-03-12
申请人： Norihiro Akiyama , Hirokazu Yanagawa , Hatsuo Motoyama
发明人： Norihiro Akiyama , Hirokazu Yanagawa , Hatsuo Motoyama
IPC分类号： G06F7/68 , H03L7/197 , H03L7/06
CPC分类号： G06F7/68 , H03L7/1976
摘要： A rational frequency division device eliminates spurious components by a simple arrangement and can set a broad frequency modulation range. A frequency synthesizer using the rational frequency division device includes an arithmetic circuit, which outputs the frequency division ratio to a frequency divider in a PLL circuit constituted by a variable frequency oscillator 4, a frequency divider 6, and a phase detector 2. The arithmetic circuit includes a plurality of series-connected cumulative adders 22 which include a first cumulative adder that receives a rational number defined by an integer value and a decimal value, an integer value extraction circuit 23 for extracting an integer value from the output value of the cumulative adder of the final stage, and a delay circuit 24 for outputting the integer value extracted by the integer value extraction circuit to the frequency divider as the frequency division ratio, and outputting the integer value to the respective cumulative adders as a feedback value. Each cumulative adder adds a value calculated by itself in the previous clock period to the input rational number or the output value from the cumulative adder of the previous stage, and subtracts the feedback value from the delay circuit therefrom, thus outputting the calculated value.
摘要翻译： PCT No.PCT / JP96 / 02143 Sec。 371日期1997年3月12日 102（e）1997年3月12日PCT PCT 1996年7月30日PCT公布。出版物WO97 / 06600 日期1997年2月20日合理的分频装置通过简单的布置消除杂散分量，并可以设置宽的频率调制范围。使用有理分频装置的频率合成器包括：运算电路，其将分频比输出到由可变频率振荡器4，分频器6和相位检测器2构成的PLL电路中的分频器。运算电路包括多个串联连接的累积加法器22，其包括接收由整数值和十进制值定义的有理数的第一累积加法器，用于从累积加法器的输出值中提取整数值的整数值提取电路23 以及用于将由整数值提取电路提取的整数值输出到分频器的延迟电路24作为分频比，并将整数值作为反馈值输出到各累积加法器。每个累积加法器将在前一时钟周期中自己计算的值与前一级的累积加法器的输入有理数或输出值相加，并从其延迟电路中减去反馈值，从而输出计算值。

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