专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06931508B2 Device and method for information processing 有权
标题翻译：信息处理的设备和方法
公开(公告)号：US06931508B2
公开(公告)日：2005-08-16
申请号：US10318115
申请日：2002-12-13
申请人： Hiroshi Okano , Fumihiko Hayakawa
发明人： Hiroshi Okano , Fumihiko Hayakawa
IPC分类号： G06F12/04 , G06F12/08 , G06F12/00
CPC分类号： G06F9/30043 , G06F9/30032 , G06F12/04 , G06F12/0886
摘要： In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to seventh selectors appropriately select either the first address or the second address, and supply the selected address to first to seventh memory areas, respectively. An eighth memory area is supplied with the first address.
摘要翻译：在信息处理装置中，第一地址加法器生成表示用于写入数据的目标的第一地址或要读取的数据的存储位置。第二地址加法器通过将8加到第一地址来产生第二地址。第一至第七选择器适当地选择第一地址或第二地址，并将选择的地址分别提供给第一至第七存储区。第八个存储区被提供有第一个地址。

2. 发明授权

US07133973B2 Arithmetic processor 失效
公开(公告)号：US07133973B2
公开(公告)日：2006-11-07
申请号：US10355075
申请日：2003-01-31
申请人： Fumihiko Hayakawa , Hiroshi Okano
发明人： Fumihiko Hayakawa , Hiroshi Okano
IPC分类号： G06G12/08
CPC分类号： G06F9/3824
摘要： An an address generator generates a read address. It is detected whether the generated read address is continuous to the read address previously generated. A cache unit control circuit controls the read data to be directly output to a requester of the read data without passing the read data through a cache RAM, if a cache miss occurs, and if it has been detected that the two addresses are continuous. As a result, the subsequent operations can executed even if the present operation has not been completed.

3. 发明授权

US07028151B2 Information processing device equipped with improved address queue register files for cache miss 失效
标题翻译：信息处理设备配备改进的地址队列寄存器文件，用于缓存未命中
公开(公告)号：US07028151B2
公开(公告)日：2006-04-11
申请号：US10643223
申请日：2003-08-19
申请人： Satoshi Imai , Fumihiko Hayakawa , Atsuhiro Suga
发明人： Satoshi Imai , Fumihiko Hayakawa , Atsuhiro Suga
IPC分类号： G06F12/00
CPC分类号： G06F12/0859
摘要： When an input address AD is previously stored in a register 211, if a matching signal EQ1 is active, then an address queue control circuit 19A latches an offset of the input address AD into a register 241, or else, latches the input address AD into a register 212 through a selector 262. When the input address AD is previously stored in the register 241, the address queue control circuit 19A latches the input address AD into the register 212 through the selector 262. After reading the contents of the register 211, the address queue control circuit 19A shifts the offset OFS of the register 241 to the offset field of the register 211 through a selector 261, and resets a valid flag EF of the register 241.
摘要翻译：当输入地址AD预先存储在寄存器211中时，如果匹配信号EQ1有效，则地址队列控制电路19A将输入地址AD的偏移锁存到寄存器241中，否则锁存输入地址 AD通过选择器262进入寄存器212。当输入地址AD预先存储在寄存器241中时，地址队列控制电路19A通过选择器262将输入地址AD锁存到寄存器212中。在读取寄存器211的内容之后，地址队列控制电路19A通过选择器261将寄存器241的偏移量OFS移位到寄存器211的偏移场，并且复位寄存器241的有效标志EF。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式