专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090268526A1 SEMICONDUCTOR MEMORY DEVICE WITH A STACKED GATE INCLUDING A CHARGE STORAGE LAYER AND A CONTROL GATE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：具有包括充电储存层的堆叠门和控制门的半导体存储器件及其控制方法
公开(公告)号：US20090268526A1
公开(公告)日：2009-10-29
申请号：US12406382
申请日：2009-03-18
申请人： Takeshi NAKANO , Hiroshi NAKAMURA , Koji HOSONO
发明人： Takeshi NAKANO , Hiroshi NAKAMURA , Koji HOSONO
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/08
摘要： A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.
摘要翻译：半导体存储器件包括转移电路和控制电路。该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到其源极施加第二电压，并且其漏极连接到负载。控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

2. 发明申请

US20100329017A1 SEMICONDUCTOR DEVICE FOR SHORT-CIRCUITING OUTPUT TERMINALS OF TWO OR MORE VOLTAGE GENERATOR CIRCUITS AT READ TIME AND CONTROL METHOD FOR THE SAME 有权
标题翻译：用于短时间读取两个或更多电压发生器电路的输出端子的半导体器件及其控制方法
公开(公告)号：US20100329017A1
公开(公告)日：2010-12-30
申请号：US12822587
申请日：2010-06-24
申请人： Takeshi NAKANO , Mikio Ogawa
发明人： Takeshi NAKANO , Mikio Ogawa
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/30
摘要： According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time.
摘要翻译：根据一个实施例，半导体器件包括第一电压发生器，第二电压发生器，第一MOS晶体管和控制器。第一电压发生器向第一节点输出第一电压。第二电压发生器向第二节点输出第二电压。第一MOS晶体管能够使第一节点和第二节点短路。控制器通过接通第一MOS晶体管来执行控制操作以使第一节点和第二节点短路。控制器基于时间控制第一MOS晶体管保持在接通状态的时段。

3. 发明申请

US20080014505A1 POLYMER ELECTROCHEMICAL DEVICE 有权
标题翻译：聚合物电化学装置
公开(公告)号：US20080014505A1
公开(公告)日：2008-01-17
申请号：US11762470
申请日：2007-06-13
申请人： Toshinori KATO , Tomohiro ONO , Shinji NAKAI , Takeshi NAKANO , Hiroyuki OGI
发明人： Toshinori KATO , Tomohiro ONO , Shinji NAKAI , Takeshi NAKANO , Hiroyuki OGI
IPC分类号： H01M2/16
CPC分类号： F03G7/005 , H01M2300/0082
摘要： This invention relates to an electrochemical device which comprises a molding containing as a main ingredient a copolymer (Z) and at least two mutually insulated electrodes in joint with the molding, wherein the copolymer (Z) comprises a polymer block (A) having as a main unit an aromatic vinyl compound unit and a polymer block (B) being incompatible with the polymer block (A), and has ion-conducting groups on the polymer block (A). The electrochemical device of the invention can be used particularly as an actuator device. The electrochemical device or actuator device of the invention can be actuated swiftly; is excellent in industrial economical efficiency; has only a low influence on the environment; holds self-standing properties; and is excellent in mechanical strength.
摘要翻译：本发明涉及一种电化学装置，该电化学装置包含以成型物为主要成分的共聚物（Z）和至少两个相互绝缘的电极，其中共聚物（Z）包含聚合物嵌段（A）主要单元是芳族乙烯基化合物单元和与聚合物嵌段（A）不相容的聚合物嵌段（B），并且在聚合物嵌段（A）上具有离子传导性基团。本发明的电化学装置可以特别用作致动装置。本发明的电化学装置或致动器装置可以迅速地致动; 工业经济效益优异; 对环境影响不大; 拥有自立的财产; 机械强度优异。

4. 发明申请

US20120325598A1 BRAKE LINING FOR RAILROAD CAR 审中-公开
标题翻译：刹车线用于铁路车辆
公开(公告)号：US20120325598A1
公开(公告)日：2012-12-27
申请号：US13605004
申请日：2012-09-06
申请人： Takanori KATO , Atsushi SAKAGUCHI , Kazutaka ASABE , Takashi MAEJIMA , Satoru NAKANO , Takeshi NAKANO
发明人： Takanori KATO , Atsushi SAKAGUCHI , Kazutaka ASABE , Takashi MAEJIMA , Satoru NAKANO , Takeshi NAKANO
IPC分类号： B61H1/00 , F16D65/097
CPC分类号： F16D65/092 , B61H5/00 , F16D69/0408 , F16D2069/0433
摘要： A brake lining for a railroad car has a frictional surface on a brake disc that is pressed by a brake caliper. Friction bodies are pressed against the frictional surface of the brake disc and a back plate is mounted to the caliper to support the friction bodies. Each of the friction bodies is formed with a friction material which contacts the brake disc frictional surface, and has a base plate attached on the back plate side of the friction material. The base plate has a protrusion formed on its back side. On the friction body side of the back plate there is formed a groove which contacts the protrusion formed on the base plate. A disc spring or a spherical-seated structure is disposed between the base plate of each friction body and the back plate. Friction bodies are prevented from rotating at their attached places, without adding new components.
摘要翻译：用于铁路车辆的制动衬片在由制动钳按压的制动盘上具有摩擦面。摩擦体被压靠在制动盘的摩擦表面上，并且背板安装在卡钳上以支撑摩擦体。每个摩擦体形成有与制动盘摩擦面接触的摩擦材料，并且具有安装在摩擦材料的背板侧的基板。基板在其背面形成有突起。在背板的摩擦体侧形成有与形成在基板上的突起接触的槽。在每个摩擦体的基板和后板之间设置盘形弹簧或球形结构。摩擦体被阻止在其附近的位置旋转，而不添加新的部件。

5. 发明申请

US20120182953A1 Mobile Communication System, Base Station Device and Frequency Allocation Method for Mobile Communication System 审中-公开
标题翻译：移动通信系统，移动通信系统的基站设备和频率分配方法
公开(公告)号：US20120182953A1
公开(公告)日：2012-07-19
申请号：US13430461
申请日：2012-03-26
申请人： Youhei MURAKAMI , Masamitsu NISHIKIDO , Takeshi NAKANO , Yutaka OOTSUKI
发明人： Youhei MURAKAMI , Masamitsu NISHIKIDO , Takeshi NAKANO , Yutaka OOTSUKI
IPC分类号： H04W72/08
CPC分类号： H04W72/085 , H04L5/0037 , H04L5/006 , H04L5/0094 , H04W68/00 , H04W72/0453 , H04W88/08
摘要： In a base station device 12 of an OFDMA mobile communication system, a frequency band storage unit 22 stores multiple frequency bands allocatable to mobile station devices, respectively, in association with predetermined conditions related to communication quality. A communication quality acquisition unit 37 acquires communication quality in communication with each of the mobile station devices. A frequency allocator 24 selects any one of the frequency bands from the frequency band storage unit 22 on the basis of the communication quality acquired by the communication quality acquisition unit 37, and notifies the mobile station device of channel information indicating the selected frequency band. Then, the mobile station device communicates with the base station device 12 in the frequency band indicated by the channel information notified by the frequency allocator 24 in the base station device 12.
摘要翻译：在OFDMA移动通信系统的基站装置12中，频带存储部22分别存储与通信质量有关的规定条件可分配给移动台装置的多个频带。通信质量获取单元37获取与每个移动站装置进行通信的通信质量。频率分配器24基于由通信质量获取单元37获取的通信质量从频带存储单元22中选择频带中的任何一个，并向移动台设备通知指示所选择的频带的信道信息。然后，移动站装置在由基站装置12中的频率分配器24通知的频道信息表示的频带中与基站装置12进行通信。

6. 发明申请

US20110317055A1 SOLID-STATE IMAGING DEVICE, CAMERA MODULE, AND IMAGING METHOD 失效
标题翻译：固态成像装置，摄像机模块和成像方法
公开(公告)号：US20110317055A1
公开(公告)日：2011-12-29
申请号：US13049334
申请日：2011-03-16
申请人： Masahiko NOZAKI , Takeshi NAKANO , Junichi HOSOKAWA
发明人： Masahiko NOZAKI , Takeshi NAKANO , Junichi HOSOKAWA
IPC分类号： H04N5/335
CPC分类号： H04N5/361
摘要： According to one embodiment, a third optical black portion is arranged in parallel with a first optical black portion in a row direction and in parallel with a second optical black portion in column direction. At least one of the vertical line correction circuit and the horizontal line correction circuit adds/subtracts arithmetic average of the third black level signal generated by the third optical black portion.
摘要翻译：根据一个实施例，第三光学黑色部分与行方向上的第一光学黑色部分平行布置，并且与列方向上的第二光学黑色部分平行布置。垂直线校正电路和水平线校正电路中的至少一个对由第三光学黑色部分产生的第三黑电平信号的算术平均值进行加/减。

7. 发明申请

US20070211530A1 DATA RECORDING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路器件的数据记录方法
公开(公告)号：US20070211530A1
公开(公告)日：2007-09-13
申请号：US11683604
申请日：2007-03-08
申请人： Takeshi NAKANO
发明人： Takeshi NAKANO
IPC分类号： G11C14/00 , G11C16/04 , G11C11/34
CPC分类号： G11C11/5628 , G06F12/0804 , G06F12/0893 , G06F2212/2022 , G11C5/025 , G11C8/10 , G11C16/0483 , G11C2211/5641 , G11C2211/5643
摘要： A data recording system of a semiconductor integrated circuit device having a memory area is disclosed. The semiconductor integrated circuit device is equipped with a memory area that includes a binary area and a multi-level area. The semiconductor integrated circuit device records, in the binary area, data transmitted from a host device as binary data. Further, when no access is provided from the host device, the semiconductor integrated circuit device copies, to the multi-level area, the data recorded in the binary area as multi-level data.
摘要翻译：公开了一种具有存储区域的半导体集成电路器件的数据记录系统。半导体集成电路器件配备有包括二进制区和多电平区的存储区。半导体集成电路装置在二进制区域中记录从主机装置发送的作为二进制数据的数据。此外，当不从主机设备提供访问时，半导体集成电路装置将记录在二进制区域中的数据复制到多级区域作为多级数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式