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1. 发明授权

US4118741A Hue adjusting circuits 失效
标题翻译：色调调节电路
公开(公告)号：US4118741A
公开(公告)日：1978-10-03
申请号：US769784
申请日：1977-02-17
申请人： Hiroshi Gomi , Shinichiro Taguchi
发明人： Hiroshi Gomi , Shinichiro Taguchi
IPC分类号： H04N9/64 , H04N9/50 , H04N9/535
CPC分类号： H04N9/643
摘要： In a circuit for processing a chroma signal the chroma signal is applied to a demodulator through a first phase shifter. The burst signal is applied to an automatic phase adjusting circuit including a phase detection circuit and a voltage-controlled oscillator. The output of the phase adjusting circuit is applied to a hue adjusting circuit including a second phase shifter and a mixing circuit connected to receive the output of the phase adjusting circuit and the output of the second phase shifter. A control voltage is applied to the mixing circuit for controlling the relative amplitude of the two inputs applied to the mixing circuit. The output of the hue adjusting circuit is applied to the demodulator to act as the subcarrier signal for demodulating the chroma signal. The first and second phase shifters are each comprised of a resistor and a capacitor and formed on the same integrated circuit semiconductor substrate.
摘要翻译：在用于处理色度信号的电路中，色度信号通过第一移相器施加到解调器。突发信号被施加到包括相位检测电路和压控振荡器的自动相位调整电路。相位调整电路的输出被施加到包括第二移相器和混合电路的色调调整电路，该混合电路被连接以接收相位调整电路的输出和第二移相器的输出。控制电压被施加到混合电路，用于控制施加到混合电路的两个输入的相对幅度。色调调整电路的输出应用于解调器，作为解调色度信号的副载波信号。第一和第二移相器各自包括电阻器和电容器，并形成在同一集成电路半导体衬底上。

2. 发明授权

US4247867A Apparatus for processing the output voltage of a detection circuit 失效
标题翻译：用于处理检测电路的输出电压的装置
公开(公告)号：US4247867A
公开(公告)日：1981-01-27
申请号：US941366
申请日：1978-09-11
申请人： Hiroshi Gomi , Shinichiro Taguchi
发明人： Hiroshi Gomi , Shinichiro Taguchi
IPC分类号： H03L7/08 , H04N9/455 , H04N9/46 , H03B3/06 , H03D3/18 , H04N9/49
CPC分类号： H03L7/08 , H04N9/455
摘要： The apparatus comprises a phase detection circuit for detecting the phase difference between two input signals to produce a single output which is supplied to charge a capacitor through a gate circuit and a unidirectionally conductive element. The terminal voltage of the capacitor is applied to one control terminal of a differential load circuit. The other control terminal of the load circuit is connected to receive the voltage produced by a bias circuit similar to the gate circuit.
摘要翻译：该装置包括用于检测两个输入信号之间的相位差的相位检测电路，以产生单个输出，该输出被提供以通过栅极电路和单向导电元件对电容器充电。电容器的端子电压施加到差分负载电路的一个控制端子。负载电路的另一个控制端子被连接以接收由类似于门电路的偏置电路产生的电压。

3. 发明授权

US09178226B2 Fuel cell sealing structure 有权
标题翻译：燃料电池密封结构
公开(公告)号：US09178226B2
公开(公告)日：2015-11-03
申请号：US13378642
申请日：2010-05-27
申请人： Takeshi Masaka , Yoshihiro Kurano , Shinichiro Taguchi , Kenichi Kikuchi , Tetsuya Urakawa
发明人： Takeshi Masaka , Yoshihiro Kurano , Shinichiro Taguchi , Kenichi Kikuchi , Tetsuya Urakawa
IPC分类号： H01M8/02 , H01M8/04 , H01M8/10
CPC分类号： H01M8/0273 , H01M8/0202 , H01M8/0247 , H01M8/0267 , H01M8/0276 , H01M8/0284 , H01M8/04029 , H01M8/1007 , Y02E60/521
摘要： A fuel cell sealing structure has a power generating body, and first and second separators arranged in both sides in a thickness direction of the power generating body. On a surface in one side in a thickness direction of the first separator, formed integrally first and second sealing protrusions respectively brought into close contact with an outer peripheral portion of the power generating body and the second separator in an outer peripheral side of the first sealing protrusion, and a short circuit prevention rib protruding in line with the first and second sealing protrusions by an electrically insulating rubber-like elastic material. On a surface in another side thereof, formed integrally a third sealing protrusion brought into close contact with a surface in an opposite side to the power generating body in the second separator, by the electrically insulating rubber-like elastic material.
摘要翻译：燃料电池密封结构具有发电体，并且在发电体的厚度方向上的两侧配置有第一和第二隔板。在第一隔板的厚度方向的一侧的表面上，一体地形成有第一密封突起和第二密封突起，分别在第一密封件的外周侧与发电体的外周部和第二隔板紧密接触突出部以及通过电绝缘橡胶状弹性材料与第一密封突起和第二密封突起一直突出的防短路肋。在其另一侧的表面上，通过电绝缘橡胶状弹性材料一体地形成与第二隔板中的发电体相反侧的表面紧密接触的第三密封突起。

4. 发明申请

US20120107718A1 FUEL CELL SEALING STRUCTURE 有权
标题翻译：燃料电池密封结构
公开(公告)号：US20120107718A1
公开(公告)日：2012-05-03
申请号：US13378642
申请日：2010-05-27
申请人： Takeshi Masaka , Yoshihiro Kurano , Shinichiro Taguchi , Kenichi Kikuchi , Tetsuya Urakawa
发明人： Takeshi Masaka , Yoshihiro Kurano , Shinichiro Taguchi , Kenichi Kikuchi , Tetsuya Urakawa
IPC分类号： H01M8/02 , H01M8/10
CPC分类号： H01M8/0273 , H01M8/0202 , H01M8/0247 , H01M8/0267 , H01M8/0276 , H01M8/0284 , H01M8/04029 , H01M8/1007 , Y02E60/521
摘要： A fuel cell sealing structure has a power generating body, and first and second separators arranged in both sides in a thickness direction of the power generating body. On a surface in one side in a thickness direction of the first separator, formed integrally first and second sealing protrusions respectively brought into close contact with an outer peripheral portion of the power generating body and the second separator in an outer peripheral side of the first sealing protrusion, and a short circuit prevention rib protruding in line with the first and second sealing protrusions by an electrically insulating rubber-like elastic material. On a surface in another side thereof, formed integrally a third sealing protrusion brought into close contact with a surface in an opposite side to the power generating body in the second separator, by the electrically insulating rubber-like elastic material.
摘要翻译：燃料电池密封结构具有发电体，并且在发电体的厚度方向上的两侧配置有第一和第二隔板。在第一隔板的厚度方向的一侧的表面上，一体地形成有第一密封突起和第二密封突起，分别在第一密封件的外周侧与发电体的外周部和第二隔板紧密接触突出部以及通过电绝缘橡胶状弹性材料与第一密封突起和第二密封突起一直突出的防短路肋。在其另一侧的表面上，通过电绝缘橡胶状弹性材料一体地形成与第二隔板中的发电体相反侧的表面紧密接触的第三密封突起。

5. 发明申请

US20120064429A1 SEALING STRUCTURE OF FUEL CELL 有权
标题翻译：密封燃料电池结构
公开(公告)号：US20120064429A1
公开(公告)日：2012-03-15
申请号：US13320886
申请日：2010-04-27
申请人： Shinichiro Taguchi , Shigeru Watanabe
发明人： Shinichiro Taguchi , Shigeru Watanabe
IPC分类号： H01M8/02 , H01M8/10
CPC分类号： H01M8/0276 , H01M8/0247 , H01M2008/1095 , Y02E60/50
摘要： A sealing structure of a fuel cell has a first gasket made of an elastomer and provided integrally on a separator, and a second gasket made of an elastomer and provided integrally on other separator. A membrane-electrode assembly is sandwiched or pinched by the first and second gaskets. The first gasket has a main lip in which a top portion brought into close contact with the membrane-electrode assembly is formed flat. The second gasket has a flat seal portion and a sub lip protruding from this flat seal portion at a position opposing the main lip. The flat seal portion and the sub lip are brought into close contact with the membrane-electrode assembly. The width of the top portion of the main lip is narrower than the width of the flat seal portion, and larger than the width of the sub lip.
摘要翻译：燃料电池的密封结构具有由弹性体制成并且一体地设置在隔板上的第一垫圈和由弹性体制成的第二垫圈，并且一体地设置在其它隔板上。膜 - 电极组件被第一和第二衬垫夹住或夹住。第一垫圈具有与膜 - 电极组件紧密接触的顶部的主唇部形成为平坦的。第二垫圈具有平坦的密封部分和从该平坦的密封部分在与主唇部相对的位置处突出的子唇缘。扁平密封部分和子唇缘与膜 - 电极组件紧密接触。主唇的顶部的宽度比扁平密封部分的宽度窄，并且大于子唇缘的宽度。

6. 发明授权

US07356721B2 Microcomputer and emulation apparatus 有权
标题翻译：微电脑和仿真设备
公开(公告)号：US07356721B2
公开(公告)日：2008-04-08
申请号：US11007298
申请日：2004-12-09
申请人： Shinichiro Taguchi , Hideaki Ishihara , Yoshinori Teshima , Naoki Ito
发明人： Shinichiro Taguchi , Hideaki Ishihara , Yoshinori Teshima , Naoki Ito
IPC分类号： G06F1/12 , G06F9/455
CPC分类号： G06F13/24
摘要： A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.
摘要翻译：单片微计算机包括逻辑电路，CPU和触发器，用于基于时钟信号将由逻辑电路提供的中断请求信号同步到CPU。多芯片仿真装置包括分别用于仿真逻辑电路，CPU和触发器的功能的外围评估芯片，CPU评估芯片和装置。当在开发中使用多芯片仿真装置来模拟单片机的功能时，用于模拟触发器的功能的装置同步中断请求信号以吸收由中断请求信号引起的延迟时间由于外围评估芯片和CPU评估芯片之间的物理距离，使得仿真中的中断处理定时与单片机的实际操作中的中断处理定时相匹配。

7. 发明授权

US4364091A Equalizing pulse removal circuit 失效
标题翻译：均衡脉冲去除电路
公开(公告)号：US4364091A
公开(公告)日：1982-12-14
申请号：US235720
申请日：1981-02-18
申请人： Shinichiro Taguchi , Nobuya Nagao , Yutaka Ogihara
发明人： Shinichiro Taguchi , Nobuya Nagao , Yutaka Ogihara
IPC分类号： H04N5/932 , H04N9/83 , H04N5/04
CPC分类号： H04N5/932 , H04N9/83
摘要： There are provided circuits for removing the equalizing pulses from the video signal. A composite sync signal separated from a video signal is applied to a gate circuit, so that only horizontal sync pulses are extracted. The gate pulse applied to the gate circuit is formed in the following manner. Clock pulses of a frequency 175/4 f.sub.H (f.sub.H : a horizontal scanning frequency and about 15,734 KHz), for example, is frequency-divided into a signal of a frequency 175/256 f.sub.H by a frequency divider. A reset circuit processes the frequency-divided output signal, the delayed sync signal and the inverted composite sync signal to form pulses in synchronism with the horizontal sync pulses. The pulses thus obtained reset the frequency divider. At the same timing of the pulse generation from the reset circuit, a gate pulse generating circuit generates pulses whose pulse widths are longer than the pulse widths of the horizontal pulses, which in turn are applied as the gate pulse to the gate circuit.
摘要翻译：提供了用于从视频信号中去除均衡脉冲的电路。与视频信号分离的复合同步信号被施加到门电路，从而仅提取水平同步脉冲。施加到栅极电路的栅极脉冲以下列方式形成。频率为175/4 fH（fH：水平扫描频率和约15,734KHz）的时钟脉冲通过分频器被分频为频率为175/256fH的信号。复位电路处理分频输出信号，延迟同步信号和反相复合同步信号，以与水平同步脉冲同步地形成脉冲。如此获得的脉冲复位分频器。在来自复位电路的脉冲产生的相同定时，栅极脉冲产生电路产生其脉冲宽度大于水平脉冲的脉冲宽度的脉冲，该脉冲宽度又作为栅极脉冲施加到栅极电路。

8. 发明授权

US07571260B2 CPU address decoding with multiple target resources 失效
标题翻译：具有多个目标资源的CPU地址解码
公开(公告)号：US07571260B2
公开(公告)日：2009-08-04
申请号：US11541771
申请日：2006-10-03
申请人： Shinichiro Taguchi , Kenji Yamada , Hideaki Ishihara
发明人： Shinichiro Taguchi , Kenji Yamada , Hideaki Ishihara
IPC分类号： G06F3/00 , G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A microcomputer includes a CPU, multiple resources, and an output circuit having an address decoder. The CPU outputs an address signal to the address decoder. The address decoder decodes the address signal and the output circuit outputs a select signal to at least one of the resources in accordance with the decoded address signal. Each of the resources is writable by the CPU when receiving the select signal. When the address signal indicates a predetermined address, the output circuit outputs the select signal to at least two of the resources at a time. Thus, data can be written to the multiple resources at a time. Therefore, the CPU can write the data to the multiple resources within a reduced time by using the output circuit.
摘要翻译：微型计算机包括CPU，多个资源以及具有地址解码器的输出电路。 CPU向地址解码器输出地址信号。地址解码器解码地址信号，并且输出电路根据解码的地址信号向至少一个资源输出选择信号。当接收到选择信号时，每个资源都可由CPU写入。当地址信号指示预定的地址时，输出电路一次向至少两个资源输出选择信号。因此，可以一次将数据写入多个资源。因此，CPU可以通过使用输出电路在减少的时间内将数据写入多个资源。

9. 发明申请

US20050188131A1 Microcomputer and emulation apparatus 有权
标题翻译：微电脑和仿真设备
公开(公告)号：US20050188131A1
公开(公告)日：2005-08-25
申请号：US11007298
申请日：2004-12-09
申请人： Shinichiro Taguchi , Hideaki Ishihara , Yoshinori Teshima , Naoki Ito
发明人： Shinichiro Taguchi , Hideaki Ishihara , Yoshinori Teshima , Naoki Ito
IPC分类号： G06F11/22 , G06F9/46 , G06F9/48 , G06F13/10 , G06F13/24
CPC分类号： G06F13/24
摘要： A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.
摘要翻译：单片微计算机包括逻辑电路，CPU和触发器，用于基于时钟信号将由逻辑电路提供的中断请求信号同步到CPU。多芯片仿真装置包括分别用于仿真逻辑电路，CPU和触发器的功能的外围评估芯片，CPU评估芯片和装置。当在开发中使用多芯片仿真装置来模拟单片机的功能时，用于模拟触发器的功能的装置同步中断请求信号以吸收由中断请求信号引起的延迟时间由于外围评估芯片和CPU评估芯片之间的物理距离，使得仿真中的中断处理定时与单片机的实际操作中的中断处理定时相匹配。

10. 发明授权

US4430674A Color video signal processing circuit 失效
标题翻译：彩色视频信号处理电路
公开(公告)号：US4430674A
公开(公告)日：1984-02-07
申请号：US238026
申请日：1981-02-25
申请人： Shinichiro Taguchi , Nobuya Nagao , Yutaka Ogihara
发明人： Shinichiro Taguchi , Nobuya Nagao , Yutaka Ogihara
IPC分类号： H04N9/793 , H04N9/49
CPC分类号： H04N9/793
摘要： DC control signals responsive to ACC voltages are applied to a color signal amplifier, to which recording and reproducing color signals are applied, to control the operation of the color signal amplifier to recording or reproducing mode. Such control is attained by using color killer signal responsive to mode changeover and ACC detector signals which serve to assign the color signal amplifier to recording or reproducing mode. Color signals are obtained from the output terminal of the color signal amplifier in both modes. In the case of recording mode, essentially undesirable recording color signals appearing to the output terminal of the color signal amplifier are by-passed by a low-pass filter, and only ACC detector voltages which are used as color killer signals are supplied to a mixer circuit which mixes brightness and color signals to generate composite color signals to be recorded. This recording signal mixer circuit serves to restrain, if necessary, low frequency converted color signals from being supplied from the recording signal mixer circuit to a recording head responsive to color killer signals. In the case of reproducing mode, color signals appearing to the output terminal of the color signal amplifier are supplied to a reproducing mixer which composes composite color signals to be reproduced from brightness and color signals to be reproduced. Input signals to the color signal amplifier are treated at the time of recording mode in such a way that color killer voltages are superposed on essentially undesirable recording color signals to extract only color killer voltages on the output terminal side of the color amplifier, thus allowing the circuit, which functions as the color amplifier at the time or reproducing mode, to serve as the circuit for treating color killer signals at the time of recording mode, or making the function of the single circuit different in reproducing and recording modes.
摘要翻译：响应于ACC电压的DC控制信号被施加到被施加记录和再现颜色信号的彩色信号放大器，以控制彩色信号放大器对记录或再现模式的操作。通过使用响应于模式切换的色彩抑制信号和用于将彩色信号放大器分配给记录或再现模式的ACC检测器信号来实现这种控制。在两种模式下，从彩色信号放大器的输出端获得彩色信号。在记录模式的情况下，出现在彩色信号放大器的输出端上的基本不希望的记录颜色信号被低通滤波器旁路，并且只有用作彩色抑制信号的ACC检测器电压被提供给混频器混合亮度和颜色信号以产生要记录的复合颜色信号的电路。如果需要，该记录信号混频器电路用于抑制从记录信号混频器电路向响应于彩色抑制信号的记录头提供低频转换的彩色信号。在再现模式的情况下，出现在彩色信号放大器的输出端的彩色信号被提供给一个再现混合器，该再现混合器构成要被再现的亮度和颜色信号被再现的合成彩色信号。输入到彩色信号放大器的信号在记录模式时被处理，使得抑制器电压叠加在基本上不希望的记录颜色信号上，以仅在彩色放大器的输出端侧提取彩色抑制电压，从而允许在时间或再现模式下用作彩色放大器的电路用作在记录模式时用于处理彩色抑制信号的电路，或者使得单个电路的功能在再现和记录模式上不同。

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