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1. 发明申请

US20070076518A1 Microcomputer 失效
标题翻译：微电脑
公开(公告)号：US20070076518A1
公开(公告)日：2007-04-05
申请号：US11541771
申请日：2006-10-03
申请人： Shinichiro Taguchi , Kenji Yamada , Hideaki Ishihara
发明人： Shinichiro Taguchi , Kenji Yamada , Hideaki Ishihara
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A microcomputer includes a CPU, multiple resources, and an output circuit having an address decoder. The CPU outputs an address signal to the address decoder. The address decoder decodes the address signal and the output circuit outputs a select signal to at least one of the resources in accordance with the decoded address signal. Each of the resources is writable by the CPU when receiving the select signal. When the address signal indicates a predetermined address, the output circuit outputs the select signal to at least two of the resources at a time. Thus, data can be written to the multiple resources at a time. Therefore, the CPU can write the data to the multiple resources within a reduced time by using the output circuit.
摘要翻译：微型计算机包括CPU，多个资源以及具有地址解码器的输出电路。 CPU向地址解码器输出地址信号。地址解码器解码地址信号，并且输出电路根据解码的地址信号向至少一个资源输出选择信号。当接收到选择信号时，每个资源都可由CPU写入。当地址信号指示预定的地址时，输出电路一次向至少两个资源输出选择信号。因此，可以一次将数据写入多个资源。因此，CPU可以通过使用输出电路在减少的时间内将数据写入多个资源。

2. 发明授权

US07571260B2 CPU address decoding with multiple target resources 失效
标题翻译：具有多个目标资源的CPU地址解码
公开(公告)号：US07571260B2
公开(公告)日：2009-08-04
申请号：US11541771
申请日：2006-10-03
申请人： Shinichiro Taguchi , Kenji Yamada , Hideaki Ishihara
发明人： Shinichiro Taguchi , Kenji Yamada , Hideaki Ishihara
IPC分类号： G06F3/00 , G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A microcomputer includes a CPU, multiple resources, and an output circuit having an address decoder. The CPU outputs an address signal to the address decoder. The address decoder decodes the address signal and the output circuit outputs a select signal to at least one of the resources in accordance with the decoded address signal. Each of the resources is writable by the CPU when receiving the select signal. When the address signal indicates a predetermined address, the output circuit outputs the select signal to at least two of the resources at a time. Thus, data can be written to the multiple resources at a time. Therefore, the CPU can write the data to the multiple resources within a reduced time by using the output circuit.
摘要翻译：微型计算机包括CPU，多个资源以及具有地址解码器的输出电路。 CPU向地址解码器输出地址信号。地址解码器解码地址信号，并且输出电路根据解码的地址信号向至少一个资源输出选择信号。当接收到选择信号时，每个资源都可由CPU写入。当地址信号指示预定的地址时，输出电路一次向至少两个资源输出选择信号。因此，可以一次将数据写入多个资源。因此，CPU可以通过使用输出电路在减少的时间内将数据写入多个资源。

3. 发明授权

US08176263B2 Memory management apparatus and method for same 有权
标题翻译：内存管理装置及方法相同
公开(公告)号：US08176263B2
公开(公告)日：2012-05-08
申请号：US12076021
申请日：2008-03-13
申请人： Kenji Yamada , Hideaki Ishihara
发明人： Kenji Yamada , Hideaki Ishihara
IPC分类号： G06F12/02
CPC分类号： G06F12/0284
摘要： A memory management apparatus uses a link list memory to manage a use area and a vacant area of a data memory. The use of the use area of the data memory by each of plural ports is restricted, and the use area of the data memory is configured to be always provided for each of the plural ports. In this manner, monopolized use of the data memory by a specific port is prevented and each of the plural ports is securely provided with the use area of the data memory under control of the memory management apparatus.
摘要翻译：存储器管理装置使用链路列表存储器来管理数据存储器的使用区域和空闲区域。通过多个端口中的每一个使用数据存储器的使用区域被限制，并且数据存储器的使用区域被配置为总是为多个端口中的每个端口提供。以这种方式，防止了特定端口对数据存储器的垄断使用，并且在存储器管理装置的控制下，多个端口中的每一个被牢固地设置有数据存储器的使用区域。

4. 发明授权

US08046615B2 Microcomputer system with reduced power consumption 有权
标题翻译：微电脑系统功耗降低
公开(公告)号：US08046615B2
公开(公告)日：2011-10-25
申请号：US12285481
申请日：2008-10-07
申请人： Shinichirou Taguchi , Kenji Yamada , Akimitsu Inoue , Hideaki Ishihara
发明人： Shinichirou Taguchi , Kenji Yamada , Akimitsu Inoue , Hideaki Ishihara
IPC分类号： G06F1/32 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3293 , Y02D10/122 , Y02D10/126
摘要： A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.
摘要翻译：除了具有主CPU的主微型计算机之外，还配置有具有子CPU和控制对主微型计算机的电力供应的电源控制部的子微型计算机。向子微型计算机提供具有较低频率的子时钟信号的子时钟部分可以在连续模式和间歇模式之间切换。当主CPU向子CPU发出操作停止通知时，子CPU识别通知，停止对主微型计算机的供电，并将子时钟部分设置为间歇模式。子CPU确定在间歇模式的周期内操作状态条件满足，子CPU将副时钟部分切换为连续模式，以重新开始向主微型计算机供电。

5. 发明授权

US07664933B2 Microcomputer and encoding system for instruction code and CPU 有权
公开(公告)号：US07664933B2
公开(公告)日：2010-02-16
申请号：US11330237
申请日：2006-01-12
申请人： Masahiro Kamiya , Hideaki Ishihara , Kenji Yamada , Tsuyoshi Yamamoto
发明人： Masahiro Kamiya , Hideaki Ishihara , Kenji Yamada , Tsuyoshi Yamamoto
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.

6. 发明申请

US20080016509A1 Microcomputer system 有权
标题翻译：微电脑系统
公开(公告)号：US20080016509A1
公开(公告)日：2008-01-17
申请号：US11819555
申请日：2007-06-28
申请人： Masahiro Kamiya , Kenji Yamada , Hideaki Ishihara
发明人： Masahiro Kamiya , Kenji Yamada , Hideaki Ishihara
IPC分类号： G06F9/46
CPC分类号： G06F11/0751 , G06F9/3802 , G06F11/0715
摘要： A microcomputer system includes a CPU, a memory, and a runaway detector. The CPU includes a controller for outputting a task information signal. The task information signal is activated, if the CPU performs the most important task at the present time. A program for the most important task is stored in the memory. The runaway detector includes an address register and a program area checker. The address register stores start and end addresses of the program area. The program area checker determines whether an execution address of the CPU is within the program area by comparing the execution address with each of the start and end addresses. The runaway detector detects a task runaway in the event of conflict between the task information signal and a result of a determination of the program area checker.
摘要翻译：微机系统包括CPU，存储器和失控检测器。 CPU包括用于输出任务信息信号的控制器。如果CPU执行当前最重要的任务，则任务信息信号被激活。最重要任务的程序存储在内存中。失控检测器包括地址寄存器和程序区检查器。地址寄存器存储程序区的开始和结束地址。程序区域检查器通过将执行地址与开始和结束地址中的每一个进行比较来确定CPU的执行地址是否在程序区域内。失控检测器在任务信息信号与程序区域检查器的确定结果之间发生冲突的情况下检测到任务失控。

7. 发明申请

US20060206746A1 Microcomputer 失效
标题翻译：微电脑
公开(公告)号：US20060206746A1
公开(公告)日：2006-09-14
申请号：US11357166
申请日：2006-02-21
申请人： Kenji Yamada , Hideaki Ishihara
发明人： Kenji Yamada , Hideaki Ishihara
IPC分类号： G06F1/04
CPC分类号： G06F1/30
摘要： A microcomputer includes a CPU, a program memory for storing a subroutine program, peripheral circuits, a clock circuit, and a voltage drop detection circuit. When the voltage drop detection circuit detects the voltage drop at the end of a power line, a frequency of a clock signal provided through the clock circuit to the CPU is divided down and a supply of a clock signal provided to the peripheral circuits is stopped. The CPU executes the subroutine program, thereby resuming the supply of the clock signal provided to the peripheral circuits.
摘要翻译：微型计算机包括CPU，用于存储子程序的程序存储器，外围电路，时钟电路和电压降检测电路。当电压降检测电路检测到电力线末端的电压降时，通过CPU的时钟电路提供的时钟信号的频率被分频，并且提供给外围电路的时钟信号的供给被停止。 CPU执行子程序，从而重新提供提供给外围电路的时钟信号。

8. 发明授权

US08127183B2 Microcomputer system 有权
标题翻译：微电脑系统
公开(公告)号：US08127183B2
公开(公告)日：2012-02-28
申请号：US11819555
申请日：2007-06-28
申请人： Masahiro Kamiya , Kenji Yamada , Hideaki Ishihara
发明人： Masahiro Kamiya , Kenji Yamada , Hideaki Ishihara
IPC分类号： G06F11/00 , G06F13/26
CPC分类号： G06F11/0751 , G06F9/3802 , G06F11/0715
摘要： A microcomputer system includes a CPU, a memory, and a runaway detector. The CPU includes a controller for outputting a task information signal. The task information signal is activated, if the CPU performs the most important task at the present time. A program for the most important task is stored in the memory. The runaway detector includes an address register and a program area checker. The address register stores start and end addresses of the program area. The program area checker determines whether an execution address of the CPU is within the program area by comparing the execution address with each of the start and end addresses. The runaway detector detects a task runaway in the event of conflict between the task information signal and a result of a determination of the program area checker.
摘要翻译：微机系统包括CPU，存储器和失控检测器。 CPU包括用于输出任务信息信号的控制器。如果CPU执行当前最重要的任务，则任务信息信号被激活。最重要任务的程序存储在内存中。失控检测器包括地址寄存器和程序区检查器。地址寄存器存储程序区的开始和结束地址。程序区域检查器通过将执行地址与开始和结束地址中的每一个进行比较来确定CPU的执行地址是否在程序区域内。失控检测器在任务信息信号与程序区域检查器的确定结果之间发生冲突的情况下检测到任务失控。

9. 发明申请

US20060161763A1 Microcomputer and encoding system for instruction code and CPU 有权
标题翻译：微机和编码系统的指令代码和CPU
公开(公告)号：US20060161763A1
公开(公告)日：2006-07-20
申请号：US11330237
申请日：2006-01-12
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Kenji Yamada , Tsuyoshi Yamamoto
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara , Kenji Yamada , Tsuyoshi Yamamoto
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.
摘要翻译：一种可以分时和并行地处理多个任务的微计算机，其中由任务之一描述的多个程序中的一个被描述为循环的特定任务，其中程序地址的增量是固定的，程序计数器可用作定时器计数器，在特定任务中描述外设功能指令，外设功能指令被设置为指示一个或多个通用寄存器作为操作数。 CPU作为一个指令执行外围功能指令，并实现由通用寄存器执行指令所需的信息，并将执行结果存储到通用寄存器中。指令代码编码系统包括操作代码和用于指示指令代码中的指令的操作目标的多个操作数，并且执行由操作对象上的操作代码指示的指令。当由多个操作数指示的操作目标被设置为执行结果不变化的组合时，执行与不同指令相对应的处理。

10. 发明授权

US07581128B2 Microcomputer selecting operating condition 失效
标题翻译：微电脑选择运行状况
公开(公告)号：US07581128B2
公开(公告)日：2009-08-25
申请号：US11357166
申请日：2006-02-21
申请人： Kenji Yamada , Hideaki Ishihara
发明人： Kenji Yamada , Hideaki Ishihara
IPC分类号： G06F1/00
CPC分类号： G06F1/30
摘要： A microcomputer includes a CPU, a program memory for storing a subroutine program, peripheral circuits, a clock circuit, and a voltage drop detection circuit. When the voltage drop detection circuit detects the voltage drop at the end of a power line, a frequency of a clock signal provided through the clock circuit to the CPU is divided down and a supply of a clock signal provided to the peripheral circuits is stopped. The CPU executes the subroutine program, thereby resuming the supply of the clock signal provided to the peripheral circuits.
摘要翻译：微计算机包括CPU，用于存储子程序的程序存储器，外围电路，时钟电路和电压降检测电路。当电压降检测电路检测到电力线末端的电压降时，通过CPU的时钟电路提供的时钟信号的频率被分频，并且提供给外围电路的时钟信号的供给被停止。 CPU执行子程序，从而重新提供提供给外围电路的时钟信号。

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