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1. 发明授权

US06427225B1 Method and apparatus for verification of a circuit layout 失效
标题翻译：用于验证电路布局的方法和装置
公开(公告)号：US06427225B1
公开(公告)日：2002-07-30
申请号：US09239148
申请日：1999-01-28
申请人： Osamu Kitada , Terutoshi Yamasaki , Hironobu Taoka
发明人： Osamu Kitada , Terutoshi Yamasaki , Hironobu Taoka
IPC分类号： G06F1750
CPC分类号： G06F17/5081 , G03F1/36
摘要： A semiconductor integrated circuit layout figure, inclusive of dimensional accuracy depending on the pattern shape, is efficiently verified with high accuracy. A layout verifying method for verifying whether or not a layout figure conforms to a design rule on the basis of vector data includes a reference vector classifying step for selecting and classifying a reference vector which serves as a reference for verification among vectors corresponding to sides, a verification object vector classifying step for selecting and classifying a object vector to be verified among the vectors corresponding to the sides and a verifying step for verifying a distance between each reference vector and the object vector to be verified selected among the vectors to be verified classified in correspondence with the direction of the reference vector.
摘要翻译：根据图案形状，包括尺寸精度的半导体集成电路布局图以高精度有效地验证。一种用于基于向量数据验证布图是否符合设计规则的布局验证方法，包括：参考矢量分类步骤，用于选择和分类参考矢量，所述参考矢量用作对应于侧面的矢量中的验证参考，验证对象矢量分类步骤，用于选择和分类对应于所述边的矢量中的待验证对象矢量;以及验证步骤，用于验证在要被验证的所述待验证矢量之间的距离，与参考矢量的方向对应。

2. 发明授权

US06484303B2 Apparatus for layout designing of semiconductor device, method of layout designing, and semiconductor device 失效
公开(公告)号：US06484303B2
公开(公告)日：2002-11-19
申请号：US09900026
申请日：2001-07-09
申请人： Osamu Kitada
发明人： Osamu Kitada
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A layout designing apparatus and a layout designing method that can improve the uniformity of the pattern density of a layout pattern in which dummy patterns are formed, and a semiconductor device manufactured using the layout designing method can be obtained. The layout designing method includes the steps of entering a plurality of circuit patterns of a semiconductor device; recognizing the positional data of the entered plurality of circuit patterns; producing a dummy pattern group including a plurality of dummy patterns, each of which being arranged per repetitive distance determined based on the recognized positional data of the circuit patterns; extracting a final dummy pattern including a dummy pattern located in a region not overlapping with the circuit patterns from the dummy pattern group; and outputting a layout pattern including the extracted final dummy pattern and the circuit patterns.

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