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1. 发明授权

US5396198A Electronic circuit device having a series connection of resistor and capacitance as a noise reducing circuit connected to a power source wiring 失效
标题翻译：具有连接到电源布线的降噪电路的电阻和电容的串联连接的电子电路装置
公开(公告)号：US5396198A
公开(公告)日：1995-03-07
申请号：US118178
申请日：1993-09-09
申请人： Hiroki Yamashita , Hiroyuki Itoh , Keiichirou Nakanishi , Tatsuya Saitoh , Tohru Kobayashi , Satoru Isomura
发明人： Hiroki Yamashita , Hiroyuki Itoh , Keiichirou Nakanishi , Tatsuya Saitoh , Tohru Kobayashi , Satoru Isomura
IPC分类号： H01L23/528 , H01L23/66 , H01P5/12 , H01P1/26
CPC分类号： H01L23/5286 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H01L2924/3011
摘要： A power source wiring supplies power to individual electronic circuits constituting an electronic circuit device. Load circuits are connected to the power source wiring within the range of an arrival time of a voltage noise occurring in the power source wiring in a time of about a half of a pulse width of a noise current at the time of the operation of the electronic circuit. Each of these load circuits includes a series circuit of a resistance and a capacitance.
摘要翻译：电源线为构成电子电路装置的各电子线路供电。负载电路在电子线路中发生的电压噪声的到达时间的范围内连接到电源布线，时间为电子操作时的噪声电流的脉冲宽度的大约一半电路。这些负载电路中的每一个都包括电阻和电容的串联电路。

2. 发明授权

US5018000A Semiconductor device using MIS capacitor 失效
标题翻译：半导体器件采用MIS电容器
公开(公告)号：US5018000A
公开(公告)日：1991-05-21
申请号：US367046
申请日：1989-06-16
申请人： Toshio Yamada , Tohru Kobayashi , Hirotaka Nishizawa , Hiroyuki Itoh , Tatsuya Saitoh
发明人： Toshio Yamada , Tohru Kobayashi , Hirotaka Nishizawa , Hiroyuki Itoh , Tatsuya Saitoh
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8222 , H01L27/06 , H03K17/60 , H03K19/003
CPC分类号： H01L27/0647
摘要： A MIS capacitor to be implemented in a semiconductor device employing various or predetermined circuits, has a dielectric side electrode which is in contact with a buried layer provided on a semiconductor substrate through a dielectric film and a buried layer-side electrode connected to the buried layer. The buried layer-side electrode of the MIS capacitor is connected to a low-impedance side of the circuit employed therewith. This structure, when connected as such, is capable of reducing the influence of noise attributed to an .alpha.-ray and thereby operating the circuit stably. The semiconductor device using a MIS capacitor invention is adaptable to an emitter follower circuit and various logic circuits for preventing malfunction resulting from .alpha.-ray radiation.
摘要翻译：在采用各种或预定电路的半导体器件中实现的MIS电容器具有通过电介质膜与设置在半导体衬底上的掩埋层接触的电介质侧电极和连接到掩埋层的掩埋层侧电极。 MIS电容器的掩埋层侧电极与使用的电路的低阻抗侧连接。当这样连接时，该结构能够减少归因于α射线的噪声的影响，从而稳定地操作电路。使用MIS电容器发明的半导体器件适用于射极跟随器电路和用于防止由α射线辐射引起的故障的各种逻辑电路。

3. 发明授权

US6034912A Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US6034912A
公开(公告)日：2000-03-07
申请号：US145076
申请日：1998-09-01
申请人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
发明人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
IPC分类号： G11C5/02 , H01L27/02 , H03K19/177
CPC分类号： H03K19/1776 , G11C5/025 , H01L27/0207 , H03K19/1774 , H03K19/17792 , H03K19/17796
摘要： A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits. Next, the clock signal is supplied to a plurality of third state clock distributing circuits equidistantly disposed from each of the second stage clock distributing circuits and then supplied to a plurality of final stage clock distributing circuits equidistantly disposed from each of the third stage clock distributing circuits. From these final stage clock distributing circuits, the clock signal is supplied to an area in whose units an internal gate array and a RAM macro cell or a logic macro cell are made replaceable with each other.
摘要翻译：半导体器件的存储部分和逻辑电路部分形成在单个半导体衬底上，其中第一逻辑电路块和第二逻辑电路块形成在不同的区域中，并且第二逻辑电路位于一对存储块之间。存储在一对存储器块中的数据被发送到第二逻辑电路块，以经由存储器外围电路进行处理。经由第二逻辑电路块中提供的输入/输出电路将数据处理的结果发送到第一逻辑电路块或外部设备。输入到半导体芯片的中心部分的时钟信号被提供给从中心部分等距设置的多个第一状态时钟分配电路，然后被提供给至少等距地从第一状态中的每个状态设置的多个第二级时钟分配电路时钟分配电路。接下来，时钟信号被提供给从每个第二级时钟分配电路等距离设置的多个第三状态时钟分配电路，然后提供给从每个第三级时钟分配电路等距设置的多个最后级时钟分配电路。从这些最终级时钟分配电路，将时钟信号提供给其单位内的内部门阵列和RAM宏小区或逻辑宏小区彼此可替换的区域。

4. 发明授权

US5898636A Semiconductor integrated circuit device with interleaved memory and logic blocks 失效
标题翻译：具有交错存储器和逻辑块的半导体集成电路器件
公开(公告)号：US5898636A
公开(公告)日：1999-04-27
申请号：US255240
申请日：1994-06-07
申请人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
发明人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
IPC分类号： G11C5/02 , H01L27/02 , H03K19/177 , H01L21/82
CPC分类号： H03K19/1776 , G11C5/025 , H01L27/0207 , H03K19/1774 , H03K19/17792 , H03K19/17796
摘要： A semiconductor integrated circuit device having a memory portion and a logic circuit portion formed with a same semiconductor substrate comprising a first logic circuit block, a second logic circuit block disposed in an area different from an area in which the first logic circuit block is disposed, and a pair of memory blocks oppositely disposed so that the second logic circuit block comes in between. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit provided on the second logic circuit block. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block.
摘要翻译：一种半导体集成电路器件，具有存储部分和形成有相同半导体衬底的逻辑电路部分，该半导体衬底包括第一逻辑电路块，布置在与设置第一逻辑电路块的区域不同的区域中的第二逻辑电路块，以及相对设置的一对存储器块，使得第二逻辑电路块在其间。存储在一对存储器块中的数据被发送到第二逻辑电路块，用于经由设置在第二逻辑电路块上的存储器外围电路进行处理。经由第二逻辑电路块中提供的输入/输出电路将数据处理的结果发送到第一逻辑电路块或外部设备。

5. 发明授权

US5341049A Integrated circuit having alternate rows of logic cells and I/O cells 失效
标题翻译：集成电路具有交替行的逻辑单元和I / O单元
公开(公告)号：US5341049A
公开(公告)日：1994-08-23
申请号：US916430
申请日：1992-07-21
申请人： Atsushi Shimizu , Satoru Isomura , Takeo Yamada , Tohru Kobayashi , Yoshuhiro Fujimura , Yuko Ito
发明人： Atsushi Shimizu , Satoru Isomura , Takeo Yamada , Tohru Kobayashi , Yoshuhiro Fujimura , Yuko Ito
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1735 , H01L27/118 , H01L2224/11
摘要： A semiconductor IC device has an input/output circuit and an internal logic circuit connected with the input/output circuit formed in a main surface of a semiconductor substrate of a generally rectangular shape. The input/output circuit is divided into at least two input/output circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in a direction substantially parallel with a pair of opposite sides of the substrate. The internal logic circuit is divided into at least three logic circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in the above-mentioned direction. Each of the input/output circuit blocks is sandwiched by and electrically connected with adjacently arranged two of the logic circuit blocks.
摘要翻译：半导体IC器件具有与形成在大致矩形形状的半导体衬底的主表面中的输入/输出电路连接的输入/输出电路和内部逻辑电路。输入/输出电路被划分为至少两个输入/输出电路块，使得由基板的主表面上的划分限定的逻辑电路块的边缘沿着与一对相对侧基本平行的方向延伸的基底。内部逻辑电路被分成至少三个逻辑电路块，使得由衬底的主表面上的划分限定的逻辑电路块的边缘沿上述方向延伸。每个输入/输出电路块被夹在相邻布置的两个逻辑电路块中并与其电连接。

6. 发明授权

US5306948A Semiconductor device and semiconductor module having auxiliary high power supplying terminals 失效
标题翻译：具有辅助高功率供电端子的半导体器件和半导体模块
公开(公告)号：US5306948A
公开(公告)日：1994-04-26
申请号：US950332
申请日：1992-09-24
申请人： Takeo Yamada , Satoru Isomura , Atsushi Shimizu , Yuko Ito , Tohru Kobayashi , Mikinori Kawaji
发明人： Takeo Yamada , Satoru Isomura , Atsushi Shimizu , Yuko Ito , Tohru Kobayashi , Mikinori Kawaji
IPC分类号： H01L21/66 , G01R1/04 , H01L23/053 , H01L23/057 , H01L23/473 , H01L23/498 , H01L25/065 , H01L23/02 , H01L23/12
CPC分类号： H01L25/0655 , G01R1/0483 , H01L23/053 , H01L23/057 , H01L23/473 , H01L23/49805 , H01L2224/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15174 , H01L2924/15312 , H01L2924/16152
摘要： Herein disclosed is a chip-carrier type semiconductor device adopting the MCC structure, in which a semiconductor pellet is mounted on the surface of the base substrate and in which mounting terminals to be connected with external terminals of the semiconductor pellet are mounted on the rear surface of the base substrate. In order to effect a test such as screening easily and inexpensively even if the mounting terminals are multiplied or miniaturized, the chip-carrier type semiconductor device adopting the MCC structure is equipped on the side surfaces of the base substrate with auxiliary terminals to be electrically connected with a plurality of external terminals which are arrayed on an element formed main surface of the semiconductor pellet.
摘要翻译：这里公开的是采用MCC结构的芯片载体型半导体器件，其中半导体芯片安装在基底表面上，并且其中与半导体芯片的外部端子连接的安装端子安装在后表面的基底。即使安装端子倍增或小型化，为了实现轻松便宜地进行测试，采用MCC结构的芯片载体型半导体器件配置在具有辅助端子的基底基板的电连接多个外部端子排列在半导体芯片的形成元件的主表面上。

7. 发明授权

US4868420A Flip-flop circuit 失效
标题翻译：触发电路
公开(公告)号：US4868420A
公开(公告)日：1989-09-19
申请号：US273729
申请日：1988-11-18
申请人： Hiroyuki Itoh , Masayoshi Yagyu , Toshio Yamada , Masaru Osanai , Akira Masaki , Mitsuo Usami , Tohru Kobayashi , Masato Hamamoto
发明人： Hiroyuki Itoh , Masayoshi Yagyu , Toshio Yamada , Masaru Osanai , Akira Masaki , Mitsuo Usami , Tohru Kobayashi , Masato Hamamoto
IPC分类号： H03K3/037 , H03K3/2885
CPC分类号： H03K3/2885 , H03K3/0375
摘要： An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to .alpha. rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as .alpha. rays and does not cause soft errors.
摘要翻译：提供一种改进的触发器电路，其防止由包含在半导体封装材料中的痕量放射性材料发射的α射线等引起的软误差的发生。触发器电路具有保持数据并产生第一逻辑信号的第一逻辑电路和产生第二逻辑信号的第二逻辑电路。逻辑门接收从第一和第二逻辑电路产生并具有相同逻辑电平的第一和第二逻辑信号。逻辑门的输出通过反馈回路输入到第一逻辑电路，反馈回路设置在第一逻辑电路的输出端和输入端之间，并包括逻辑门。根据本发明的电路结构，可以实现对诸如α射线的放射线的耐受性并且不引起软错误的触发器电路。

8. 发明授权

US4942320A Transistor circuit with improved .alpha. ray resistant properties 失效
标题翻译：具有改进的抗α射线特性的晶体管电路
公开(公告)号：US4942320A
公开(公告)日：1990-07-17
申请号：US208118
申请日：1988-06-17
申请人： Hiroyuki Itoh , Toshio Yamada , Akira Masaki , Tohru Kobayashi
发明人： Hiroyuki Itoh , Toshio Yamada , Akira Masaki , Tohru Kobayashi
IPC分类号： H03K17/16 , H03K19/003 , H03K19/086
CPC分类号： H03K17/16 , H03K19/0033 , H03K19/086
摘要： A transistor circuit of this invention comprises a first transistor for receiving a first bias at its base, resistor means connected to the collector of the first transistor and clamp means connected to the junction between the first transistor and the resistor means, and obtains an output from a terminal of the resistor on the opposite to its junction with the first transistor. When a noise current due to .alpha. rays develops in the first transistor and the output is lowered, the clamp means operates in such a manner that the current flows through the clamp means and prevents the change of the output. The transistor circuit of this invention is connected to a resistor or a transistor and operates as a constant current circuit for supplying a current to the resistor or the transistor so that the current flowing therethrough becomes constant. For example, it is used as a constant current source of an emitter follower to constitute a level shift circuit. It is disposed in a feedback part and used as a constant current source in a logic circuit comprising a logic part consisting of a differential transistor circuit and the feedback part for negatively feeding back the in-phase output of the differential transistor circuit.
摘要翻译：本发明的晶体管电路包括用于在其基极处接收第一偏压的第一晶体管，连接到第一晶体管的集电极的电阻器件和连接到第一晶体管和电阻器装置之间的结的钳位装置，电阻器的端子与其与第一晶体管的连接相对。当在第一晶体管中产生由于α射线引起的噪声电流并且输出降低时，钳位装置以使得电流流过钳位装置并防止输出变化的方式工作。本发明的晶体管电路连接到电阻器或晶体管，并作为恒流电路用于向电阻器或晶体管提供电流，使得流过其中的电流恒定。例如，它被用作射极跟随器的恒流源来构成电平移位电路。它被布置在反馈部分中，并在逻辑电路中用作恒流源，该逻辑电路包括由差分晶体管电路和反馈部分组成的逻辑部分，用于对差分晶体管电路的同相输出进行负反馈。

9. 发明授权

US09022793B2 Lever type connector 有权
标题翻译：杠杆式连接器
公开(公告)号：US09022793B2
公开(公告)日：2015-05-05
申请号：US13808140
申请日：2011-07-19
申请人： Tohru Kobayashi , Shoji Yamamoto
发明人： Tohru Kobayashi , Shoji Yamamoto
IPC分类号： H01R13/62 , H01R13/629 , H01R13/52 , H01R13/64
CPC分类号： H01R13/6295 , H01R13/5213 , H01R13/62938 , H01R13/62955 , H01R13/64
摘要： There is provided a lever type connector. In the lever type connector in which an electric wire cover is attached to a connector housing to which a lever is already fitted, a false fitting preventing projection that protrudes from the electric wire cover and prevents the false fitting of the electric wire cover when this projection comes into contact with the lever is provided, and the false fitting preventing projection protrudes outward rather than the connector housing and an outer surface of the lever. The false fitting preventing projection absorbs an impact applied from the outside, and serves as a cushioning member against at least the connector housing.
摘要翻译：提供了一个杠杆式连接器。在将电线罩安装在已经安装有杠杆的连接器壳体上的杠杆式连接器中，设置从电线罩突出的防错突起突起，防止当该突起设置有接触杆，并且防错突起突出部向外突出，而不是连接器壳体和杆的外表面。防伪突起防止突起吸收从外部施加的冲击，并且用作抵抗至少连接器壳体的缓冲构件。

10. 发明授权

US08979560B2 Lever type connector 有权
标题翻译：杠杆式连接器
公开(公告)号：US08979560B2
公开(公告)日：2015-03-17
申请号：US13808136
申请日：2011-07-07
申请人： Tohru Kobayashi , Tohru Suzuki
发明人： Tohru Kobayashi , Tohru Suzuki
IPC分类号： H01R13/62 , H01R13/629
CPC分类号： H01R13/62955 , H01R13/62933 , H01R13/62938
摘要： A lever type connector in which workability in inserting terminals is enhanced is provided. A lever type connector 1 includes a connector housing 22 for containing terminals 61 at terminal ends of wires, and a lever 30 which is rotatably mounted on the connector housing 22, and rotated at a wire extending side of the connector housing 22 thereby to move a mating connector to be engaged with the connector housing 22 up to a normally engaged position. The lever 30 includes a pair of arm parts 31 (31a, 31b), and a connecting part 38 for interconnecting respective base end parts 51 (51a, 51b) of the arm parts 31. A recess part 53 for enlarging a distance between the base end parts 51 is provided on at least one of inner walls 50 (50a, 50b) of the base end parts 51 of the arm parts 31 which are opposed to each other.
摘要翻译：提供了一种提高了插入端子的可加工性的杠杆式连接器。杠杆式连接器1包括用于在电线的末端容纳端子61的连接器壳体22和可旋转地安装在连接器壳体22上并在连接器壳体22的线延伸侧旋转的杆30，从而移动配合连接器将与连接器壳体22接合直到正常接合位置。杆30包括一对臂部31（31a，31b）和用于互连臂部31的各个基端部51（51a，51b）的连接部38.用于扩大基部之间的距离的凹部53 端部51设置在彼此相对的臂部31的基端部51的至少一个内壁50（50a，50b）上。

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