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1. 发明申请

US20110215435A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110215435A1
公开(公告)日：2011-09-08
申请号：US13038349
申请日：2011-03-01
申请人： Hiroki WAKIMOTO , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
发明人： Hiroki WAKIMOTO , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
IPC分类号： H01L29/06 , H01L21/78 , H01L21/302
CPC分类号： H01L21/308 , H01L21/302 , H01L21/78 , H01L29/06
摘要： Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
摘要翻译：本发明的一些实施例涉及能够防止电特性劣化的半导体器件和半导体器件的制造方法。 p型集电极区域设置在n型漂移区域的背面的表面层上。在元件的末端提供了用于获得反向阻挡能力的p +型隔离层。此外，设置从n型漂移区的背面向p +型隔离层延伸的凹部。提供p型区域并且电连接到p +型隔离层。提供p +型隔离层，以便包括具有作为一侧的凹部的底部和侧壁之间的边界的解理面。

2. 发明授权

US08604584B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08604584B2
公开(公告)日：2013-12-10
申请号：US13038349
申请日：2011-03-01
申请人： Hiroki Wakimoto , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
发明人： Hiroki Wakimoto , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
IPC分类号： H01L21/78 , H01L21/302
CPC分类号： H01L21/308 , H01L21/302 , H01L21/78 , H01L29/06
摘要： Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
摘要翻译：本发明的一些实施例涉及能够防止电特性劣化的半导体器件和半导体器件的制造方法。 p型集电极区域设置在n型漂移区域的背面的表面层上。在元件的末端提供了用于获得反向阻挡能力的p +型隔离层。此外，设置从n型漂移区的背面向p +型隔离层延伸的凹部。提供p型区域并且电连接到p +型隔离层。提供p +型隔离层，以便包括具有作为一侧的凹部的底部和侧壁之间的边界的解理面。

3. 发明申请

US20140162413A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140162413A1
公开(公告)日：2014-06-12
申请号：US14233147
申请日：2011-07-15
申请人： Hiroki Wakimoto , Masaaki Ogino
发明人： Hiroki Wakimoto , Masaaki Ogino
IPC分类号： H01L29/66
CPC分类号： H01L29/66325 , H01L21/3083 , H01L21/761 , H01L21/78 , H01L29/0619 , H01L29/0646 , H01L29/0661 , H01L29/66333
摘要： A method includes forming on a first main surface of a semiconductor wafer of a first conduction type, a gate electrode of a semiconductor element, an edge termination region for forming a breakdown voltage of the semiconductor element, and a first semiconductor region of a second conduction type which surrounds the semiconductor element and the edge termination region. A groove may be formed to reach the first semiconductor region from a second main surface of the semiconductor wafer. The groove is formed so that a portion of the semiconductor wafer, that forms an outer circumferential end of the semiconductor wafer, remains and the groove is further towards a center of the semiconductor wafer than the outer circumferential end. A third semiconductor region of the second conduction type is on a side wall of the groove and electrically connects the first semiconductor region and a second semiconductor region.
摘要翻译：一种方法包括在第一导电类型的半导体晶片的第一主表面，半导体元件的栅电极，用于形成半导体元件的击穿电压的边缘终端区域和第二导电的第一半导体区域围绕半导体元件和边缘终止区域的类型。可以形成沟槽，以从半导体晶片的第二主表面到达第一半导体区域。形成凹槽，使得形成半导体晶片的外周端的半导体晶片的一部分保留，并且凹槽比外周端更向着半导体晶片的中心。第二导电类型的第三半导体区域位于沟槽的侧壁上，并电连接第一半导体区域和第二半导体区域。

4. 发明授权

US08399309B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08399309B2
公开(公告)日：2013-03-19
申请号：US13109660
申请日：2011-05-17
申请人： Masaaki Ogino , Hiroki Wakimoto , Masayuki Miyazaki
发明人： Masaaki Ogino , Hiroki Wakimoto , Masayuki Miyazaki
IPC分类号： H01L21/00
CPC分类号： H01L29/66333 , H01L29/045 , H01L29/0657
摘要： A manufacturing method is disclosed which ensures strength of a wafer and improves device performance. A thermal diffusion layer is formed from a front surface of a wafer. A tapered groove which reaches the thermal diffusion layer is formed from a back surface by anisotropic etching with alkaline solution. In-groove thermal diffusion layer is formed on side wall surfaces of the groove. A separation layer of a reverse blocking IGBT is configured of the thermal diffusion layer and the in-groove diffusion layer. The thermal diffusion layer is formed shallowly by forming the in-groove diffusion layer. It is possible to considerably reduce thermal diffusion time. By carrying out an ion implantation forming the in-groove diffusion layer and an ion implantation forming a collector layer separately, it is possible to select an optimum value for tradeoff between turn-on voltage and switching loss, while ensuring reverse blocking voltage of the reverse blocking IGBT.
摘要翻译：公开了一种确保晶片强度并提高器件性能的制造方法。热扩散层由晶片的前表面形成。通过各向异性蚀刻用碱性溶液从后表面形成到达热扩散层的锥形槽。槽内热扩散层形成在槽的侧壁面上。反向阻断IGBT的分离层由热扩散层和内槽扩散层构成。通过形成内槽扩散层来形成浅扩散层。可以显着地减少热扩散时间。通过进行形成槽内扩散层的离子注入和分离形成集电极的离子注入，可以选择用于折合导通电压和开关损耗之间的最优值，同时确保反向的反向阻断电压阻断IGBT。

5. 发明授权

US09240456B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09240456B2
公开(公告)日：2016-01-19
申请号：US14233147
申请日：2011-07-15
申请人： Hiroki Wakimoto , Masaaki Ogino
发明人： Hiroki Wakimoto , Masaaki Ogino
IPC分类号： H01L21/332 , H01L29/66 , H01L21/761 , H01L21/78 , H01L21/308 , H01L29/06
CPC分类号： H01L29/66325 , H01L21/3083 , H01L21/761 , H01L21/78 , H01L29/0619 , H01L29/0646 , H01L29/0661 , H01L29/66333
摘要： A method includes forming on a first main surface of a semiconductor wafer of a first conduction type, a gate electrode of a semiconductor element, an edge termination region for forming a breakdown voltage of the semiconductor element, and a first semiconductor region of a second conduction type which surrounds the semiconductor element and the edge termination region. A groove may be formed to reach the first semiconductor region from a second main surface of the semiconductor wafer. The groove is formed so that a portion of the semiconductor wafer, that forms an outer circumferential end of the semiconductor wafer, remains and the groove is further towards a center of the semiconductor wafer than the outer circumferential end. A third semiconductor region of the second conduction type is on a side wall of the groove and electrically connects the first semiconductor region and a second semiconductor region.
摘要翻译：一种方法包括在第一导电类型的半导体晶片的第一主表面，半导体元件的栅电极，用于形成半导体元件的击穿电压的边缘终端区域和第二导电的第一半导体区域围绕半导体元件和边缘终止区域的类型。可以形成沟槽，以从半导体晶片的第二主表面到达第一半导体区域。形成凹槽，使得形成半导体晶片的外周端的半导体晶片的一部分保留，并且凹槽比外周端更向着半导体晶片的中心。第二导电类型的第三半导体区域位于沟槽的侧壁上，并电连接第一半导体区域和第二半导体区域。

6. 发明申请

US20140001487A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US20140001487A1
公开(公告)日：2014-01-02
申请号：US14005256
申请日：2011-09-13
申请人： Haruo Nakazawa , Masaaki Ogino , Tsunehiro Nakajima
发明人： Haruo Nakazawa , Masaaki Ogino , Tsunehiro Nakajima
IPC分类号： H01L29/739 , H01L29/66
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/0495 , H01L21/6835 , H01L21/78 , H01L29/0657 , H01L29/0661 , H01L29/0834 , H01L29/1608 , H01L29/2003 , H01L29/41741 , H01L29/47 , H01L29/475 , H01L29/66068 , H01L29/66333 , H01L29/66348 , H01L29/7395 , H01L29/7396 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68381
摘要： A semiconductor device and its method of manufacture. In the method, a front surface element structure is formed on a front surface of a semiconductor wafer, for example an SiC wafer. Then, a supporting substrate is bonded to wafer's front surface through an adhesive. The wafer's rear surface is ground and polished to thin it, with the supporting substrate bonded to the wafer. Next a V groove passing through the SiC wafer and reaching the adhesive is formed in the wafer's rear surface, and the wafer is cut into individual chips. An electrode film is formed on the groove's side wall and the chip's rear surface and a Schottky junction is formed between a drift layer, which is the chip, and the film. Then, the film is annealed. A tape is attached to the wafer's rear surface which has been cut into the chips. Then, the supporting substrate peels off from the wafer.
摘要翻译：一种半导体器件及其制造方法。在该方法中，在半导体晶片（例如SiC晶片）的前表面上形成前表面元件结构。然后，通过粘合剂将支撑基板粘合到晶片的前表面。将晶片的后表面研磨并抛光，使其支撑基板粘结到晶片上。接下来，在晶片的后表面形成通过SiC晶片并到达粘合剂的V沟槽，将晶片切割成单独的芯片。在槽的侧壁和芯片的后表面上形成电极膜，在作为芯片的漂移层与膜之间形成肖特基结。然后，将膜退火。带子被连接到已经切入芯片的晶片的后表面上。然后，支撑基板从晶片剥离。

7. 发明授权

US08999768B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08999768B2
公开(公告)日：2015-04-07
申请号：US14005256
申请日：2011-09-13
申请人： Haruo Nakazawa , Masaaki Ogino , Tsunehiro Nakajima
发明人： Haruo Nakazawa , Masaaki Ogino , Tsunehiro Nakajima
IPC分类号： H01L21/332 , H01L29/739 , H01L21/683 , H01L29/66 , H01L29/06 , H01L29/16 , H01L29/47 , H01L29/08 , H01L29/20
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/0495 , H01L21/6835 , H01L21/78 , H01L29/0657 , H01L29/0661 , H01L29/0834 , H01L29/1608 , H01L29/2003 , H01L29/41741 , H01L29/47 , H01L29/475 , H01L29/66068 , H01L29/66333 , H01L29/66348 , H01L29/7395 , H01L29/7396 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68381
摘要： A semiconductor device and its method of manufacture. In the method, a front surface element structure is formed on a front surface of a semiconductor wafer, for example an SiC wafer. Then, a supporting substrate is bonded to wafer's front surface through an adhesive. The wafer's rear surface is ground and polished to thin it, with the supporting substrate bonded to the wafer. Next a V groove passing through the SiC wafer and reaching the adhesive is formed in the wafer's rear surface, and the wafer is cut into individual chips. An electrode film is formed on the groove's side wall and the chip's rear surface and a Schottky junction is formed between a drift layer, which is the chip, and the film. Then, the film is annealed. A tape is attached to the wafer's rear surface which has been cut into the chips. Then, the supporting substrate peels off from the wafer.
摘要翻译：一种半导体器件及其制造方法。在该方法中，在半导体晶片（例如SiC晶片）的前表面上形成前表面元件结构。然后，通过粘合剂将支撑基板粘合到晶片的前表面。将晶片的后表面研磨并抛光，使其支撑基板粘结到晶片上。接下来，在晶片的后表面形成通过SiC晶片并到达粘合剂的V沟槽，将晶片切割成单独的芯片。在槽的侧壁和芯片的后表面上形成电极膜，在作为芯片的漂移层与膜之间形成肖特基结。然后，将膜退火。带子被连接到已经切入芯片的晶片的后表面上。然后，支撑基板从晶片剥离。

8. 发明授权

US5501908A Rubber composition and transmission belt using the same 失效
标题翻译：橡胶组合物和传动带使用相同
公开(公告)号：US5501908A
公开(公告)日：1996-03-26
申请号：US206835
申请日：1994-03-07
申请人： Tsutomu Shioyama , Naoki Hamano , Masaaki Ogino
发明人： Tsutomu Shioyama , Naoki Hamano , Masaaki Ogino
IPC分类号： C08K7/02 , C08L21/00 , C08L23/34 , C08L77/00 , F16G5/20 , F16G1/08 , F16G1/04 , F16G5/06 , B32B25/02
CPC分类号： F16G5/20 , C08L11/00 , C08L21/00 , C08L23/34 , C08L9/02 , C08K7/02 , C08L2205/16 , C08L2312/00 , C08L77/00 , Y10T428/249933 , Y10T428/2915 , Y10T428/2969
摘要： A rubber composition containing a rubber forming a continuous phase of 100 weight parts; a nylon fiber with fine diameter of 1-15 weight parts by the fiber, the nylon fiber being grafted with a molecular of a rubber capable of co-crosslinking to the rubber forming the continuous phase; and a short fiber of 1-30 weight parts is used to at least a part of a rubber of a transmission belt. Thus, high anisotropy in modulus of elasticity in the transmission belt is maintained. Further, stress concentration at an interface of the short fiber and the rubber is distributed to enhance the strength, elasticity and flex fatigue resistance.
摘要翻译：一种含有形成100重量份连续相的橡胶的橡胶组合物; 纤维的纤维直径为1-15重量份的尼龙纤维，尼龙纤维与能够与形成连续相的橡胶共交联的橡胶分子接枝; 并且使用1-30重量份的短纤维作为传动带的橡胶的至少一部分。因此，保持传动带中弹性模量的高各向异性。此外，短纤维和橡胶的界面处的应力集中分布，以提高强度，弹性和抗挠曲疲劳性。

9. 发明授权

US4926902A Pressure equalizer valve device of fuel injection pump 失效
标题翻译：燃油喷射泵压力均衡阀装置
公开(公告)号：US4926902A
公开(公告)日：1990-05-22
申请号：US298104
申请日：1989-01-17
申请人： Hisashi Nakamura , Satoshi Takahashi , Takayuki Ikeda , Masaaki Ogino
发明人： Hisashi Nakamura , Satoshi Takahashi , Takayuki Ikeda , Masaaki Ogino
IPC分类号： F02M59/46
CPC分类号： F02M59/462 , Y10T137/7774 , Y10T137/7777 , Y10T137/778
摘要： A pressure equalizer valve device incorporated in a fuel delivery valve assembly for use in a fuel injection pump, the fuel delivery valve assembly having a valve chamber and a delivery valve member axially movable in part within the valve chamber, the pressure equalizer valve device including a hollow equalizer valve casing member secured to the delivery valve member and having a valve seat surface portion, an equalizer valve element movable into and out of a position seated on the valve seat surface portion, a spring seat member engaging the equalizer valve element, and a helical compression spring seated at one end on the spring seat member and at the other within the delivery valve member, wherein the equalizer valve element, the spring seat member and the spring are all accommodated within the equalizer valve casing member.

10. 发明申请

US20070184617A1 Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070184617A1
公开(公告)日：2007-08-09
申请号：US10599747
申请日：2005-03-04
申请人： Masaaki Ogino , Yoshiyuki Sugahara
发明人： Masaaki Ogino , Yoshiyuki Sugahara
IPC分类号： H01L21/336 , H01L21/76 , H01L21/31
CPC分类号： H01L29/513 , H01L21/28194 , H01L21/28211 , H01L29/66181 , H01L29/66704
摘要： There is provided a semiconductor device having a high breakdown voltage and a high reliability in which a gate insulating film having a film thickness of good uniformity is formed inside a trench. An HTO is formed on an inner wall of a trench in an Si substrate by a reduced pressure CVD method and, thereafter, a thermally oxidized film is formed on an interface between the HTO and the Si substrate by performing a thermal oxidation treatment (Samples A and C). By performing these procedures as described above, the gate insulating film in which local thinning of the film is suppressed, film thickness is of good uniformity and an interface state density is low can be formed inside the trench. A semiconductor device, which has a trench gate structure, of a high quality and a high reliability having no reduction in the breakdown voltage in which a lifetime comes to be substantially longer compared with that (Sample B) in which the gate insulating film is formed only with a thermally oxidized film can be realized.
摘要翻译：提供了具有高击穿电压和高可靠性的半导体器件，其中在沟槽内形成具有良好均匀性的膜厚度的栅极绝缘膜。通过减压CVD法在Si衬底中的沟槽的内壁上形成HTO，然后通过进行热氧化处理（样品A（A））在HTO和Si衬底之间的界面上形成热氧化膜和C）。通过进行如上所述的工序，能够在沟槽内部形成抑制膜的局部变薄，膜厚均匀性高，界面态密度低的栅极绝缘膜。与形成栅极绝缘膜的（样品B）相比，具有沟槽栅极结构的半导体器件具有高质量和高可靠性，其寿命没有降低，其中寿命变得更长，只能使用热氧化膜。

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