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1. 发明申请

US20090170333A1 SHALLOW TRENCH ISOLATION ETCH PROCESS 失效
标题翻译： SHOWOW TRENCH隔离蚀刻工艺
公开(公告)号：US20090170333A1
公开(公告)日：2009-07-02
申请号：US12325220
申请日：2008-11-30
申请人： Hiroki Sasano , Meihua Shen , Radhika Mani , Sunil Srinivasan , Daehee Weon , Nicolas Gani , Shashank Deshmukh , Anisul Khan
发明人： Hiroki Sasano , Meihua Shen , Radhika Mani , Sunil Srinivasan , Daehee Weon , Nicolas Gani , Shashank Deshmukh , Anisul Khan
IPC分类号： H01L21/302
CPC分类号： H01L21/3065 , H01L21/76224
摘要： Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.
摘要翻译：本文提供了制造一个或多个浅沟槽隔离（STI）结构的方法。在一些实施例中，用于制造一个或多个浅沟槽隔离（STI）结构的方法可以包括提供具有设置在其上以限定一个或多个STI结构的图案化掩模层的衬底。可以使用由工艺气体混合物形成的等离子体来蚀刻衬底，以在衬底上形成一个或多个STI结构，其中工艺气体混合物包含含氟气体和含氟烃气体或含氢氟烃的气体。

2. 发明授权

US08133817B2 Shallow trench isolation etch process 失效
标题翻译：浅沟槽隔离蚀刻工艺
公开(公告)号：US08133817B2
公开(公告)日：2012-03-13
申请号：US12325220
申请日：2008-11-30
申请人： Hiroki Sasano , Meihua Shen , Radhika Mani , Sunil Srinivasan , Daehee Weon , Nicolas Gani , Shashank Deshmukh , Anisul Khan
发明人： Hiroki Sasano , Meihua Shen , Radhika Mani , Sunil Srinivasan , Daehee Weon , Nicolas Gani , Shashank Deshmukh , Anisul Khan
IPC分类号： H01L21/302
CPC分类号： H01L21/3065 , H01L21/76224
摘要： Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.
摘要翻译：本文提供了制造一个或多个浅沟槽隔离（STI）结构的方法。在一些实施例中，用于制造一个或多个浅沟槽隔离（STI）结构的方法可以包括提供具有设置在其上以限定一个或多个STI结构的图案化掩模层的衬底。可以使用由工艺气体混合物形成的等离子体来蚀刻衬底，以在衬底上形成一个或多个STI结构，其中工艺气体混合物包含含氟气体和含氟烃气体或含氢氟烃的气体。

3. 发明授权

US08722547B2 Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries 有权
标题翻译：用BC13基蚀刻化学法在高温下蚀刻具有高含氧层的高K电介质
公开(公告)号：US08722547B2
公开(公告)日：2014-05-13
申请号：US11736562
申请日：2007-04-17
申请人： Radhika Mani , Nicolas Gani , Wei Liu , Meihua Shen , Shashank C. Deshmukh
发明人： Radhika Mani , Nicolas Gani , Wei Liu , Meihua Shen , Shashank C. Deshmukh
IPC分类号： H01L21/31 , H01L21/311 , H01L29/51
CPC分类号： H01L21/31116 , H01L21/31122 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.
摘要翻译：在电感耦合等离子体处理室中蚀刻具有高K电介质层和含氧化物或氮化物层的晶片，通过施加源电力来产生电感耦合等离子体，将包含BCl 3的气体引入室中，设定晶片的温度在100℃至350℃之间，并且以大于10:1的氧化物或氮化物的高K电介质的选择性蚀刻晶片。具有氧化物层和氮化物层的晶片通过向晶片施加偏置功率而在反应离子蚀刻处理室中被蚀刻，将包括BCl 3的气体引入室中，将晶片的温度设定在20℃至并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。在电感耦合等离子体处理室中蚀刻具有氧化物层和氮化物层的晶片，通过向晶片施加偏置功率，施加源电力以产生电感耦合等离子体，将包括BCl 3的气体引入室中，晶片的温度在20℃和200℃之间，并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。

4. 发明授权

US07910488B2 Alternative method for advanced CMOS logic gate etch applications 失效
标题翻译：先进的CMOS逻辑门蚀刻应用的替代方法
公开(公告)号：US07910488B2
公开(公告)日：2011-03-22
申请号：US11777259
申请日：2007-07-12
申请人： Nicolas Gani , Meihua Shen , Shashank Deshmukh
发明人： Nicolas Gani , Meihua Shen , Shashank Deshmukh
IPC分类号： H01L21/302
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/31122 , H01L21/823828 , H01L29/517
摘要： Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.
摘要翻译：本文提供了用于制造CMOS逻辑门的蚀刻方法。在一些实施例中，蚀刻方法包括（a）提供具有第一堆叠和设置在其上的第二堆叠的衬底，第一堆叠包括高k电介质层，形成在高k电介质层上的金属层，以及形成在所述金属层上的第一多晶硅层，所述第二堆叠包括第二多晶硅层，其中所述第一和第二堆叠体的厚度基本相等; （b）同时蚀刻第一多晶硅层中的第一特征和第二多晶硅层中的第二特征，直到第一堆叠中的金属层暴露; （c）同时蚀刻金属层和第二多晶硅层以将相应的第一和第二特征延伸到第一和第二堆叠中; 和（d）蚀刻高k电介质层。

5. 发明申请

US20090017633A1 ALTERNATIVE METHOD FOR ADVANCED CMOS LOGIC GATE ETCH APPLICATIONS 失效
标题翻译：高级CMOS逻辑门控应用的替代方法
公开(公告)号：US20090017633A1
公开(公告)日：2009-01-15
申请号：US11777259
申请日：2007-07-12
申请人： NICOLAS GANI , Meihua Shen , Shashank Deshmukh
发明人： NICOLAS GANI , Meihua Shen , Shashank Deshmukh
IPC分类号： H01L21/302
CPC分类号： H01L21/32137 , H01L21/31116 , H01L21/31122 , H01L21/823828 , H01L29/517
摘要： Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.
摘要翻译：本文提供了用于制造CMOS逻辑门的蚀刻方法。在一些实施例中，蚀刻方法包括（a）提供具有第一堆叠和设置在其上的第二堆叠的衬底，第一堆叠包括高k电介质层，形成在高k电介质层上的金属层，以及形成在所述金属层上的第一多晶硅层，所述第二堆叠包括第二多晶硅层，其中所述第一和第二堆叠体的厚度基本相等; （b）同时蚀刻第一多晶硅层中的第一特征和第二多晶硅层中的第二特征，直到第一堆叠中的金属层暴露; （c）同时蚀刻金属层和第二多晶硅层以将相应的第一和第二特征延伸到第一和第二堆叠中; 和（d）蚀刻高k电介质层。

6. 发明申请

US20070249182A1 ETCHING OF SiO2 WITH HIGH SELECTIVITY TO Si3N4 AND ETCHING METAL OXIDES WITH HIGH SELECTIVITY TO SiO2 AT ELEVATED TEMPERATURES WITH BCl3 BASED ETCH CHEMISTRIES 有权
标题翻译：对具有高选择性的Si 3 N 4的SiO 2和具有高选择性的金属氧化物的蚀刻在基于BCl3的蚀刻化学的高温下
公开(公告)号：US20070249182A1
公开(公告)日：2007-10-25
申请号：US11736562
申请日：2007-04-17
申请人： Radhika Mani , Nicolas Gani , Wei Liu , Meihua Shen , Shashank C. Deshmukh
发明人： Radhika Mani , Nicolas Gani , Wei Liu , Meihua Shen , Shashank C. Deshmukh
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L21/31116 , H01L21/31122 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.
摘要翻译：具有高K电介质层和含氧化物或氮化物的层的晶片在电感耦合等离子体处理室中被蚀刻，通过施加源功率以产生电感耦合等离子体，将包含BCl 3 >，将晶片的温度设置在100℃和350℃之间，并且以大于10:1的氧化物或氮化物的高K电介质的选择性蚀刻晶片。具有氧化物层和氮化物层的晶片通过向晶片施加偏置功率而在反应离子蚀刻处理室中进行蚀刻，将包含BCl 3 3的气体引入室中，设定晶片的温度在20℃和200℃之间，并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。在电感耦合等离子体处理室中蚀刻具有氧化物层和氮化物层的晶片，通过向晶片施加偏置功率，施加源电力以产生电感耦合等离子体，将包括BCI 3，将晶片的温度设定在20℃至200℃之间，并以大于10:1的氧化物至氮化物选择性蚀刻晶片。

7. 发明申请

US20070281477A1 Process for etching tungsten silicide overlying polysilicon particularly in a flash memory 失效
标题翻译：用于蚀刻覆盖多晶硅的硅化钨的工艺，特别是在闪速存储器中
公开(公告)号：US20070281477A1
公开(公告)日：2007-12-06
申请号：US11445709
申请日：2006-06-02
申请人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank Deshmukh , Meihua Shen , Thorsten Lill , Jae Yu
发明人： Kyeong-Tae Lee , Jinhan Choi , Bi Jang , Shashank Deshmukh , Meihua Shen , Thorsten Lill , Jae Yu
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L21/32136 , H01L21/28273 , H01L21/32137
摘要： A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.
摘要翻译：在多晶硅上等离子体蚀刻钨硅化物的方法，特别可用于制造具有密集填充区域和开放（iso）区域的闪存，其需要由于微负载而长时间过蚀刻。在过蚀刻中晶片偏置减小。主要的蚀刻剂包括NF 3和Cl 2。加入氩气以防止在密/异界面处的底切。氧和氮氧化任何暴露的硅以提高蚀刻选择性并矫正蚀刻轮廓。可以加入SiCl 4 4以获得额外的选择性。

8. 发明申请

US20070224813A1 Device and method for etching flash memory gate stacks comprising high-k dielectric 有权
标题翻译：用于蚀刻包括高k电介质的闪存存储器栅极堆叠的器件和方法
公开(公告)号：US20070224813A1
公开(公告)日：2007-09-27
申请号：US11386054
申请日：2006-03-21
申请人： Meihua Shen , Xikun Wang , Wei Liu , Yan Du , Shashank Deshmukh
发明人： Meihua Shen , Xikun Wang , Wei Liu , Yan Du , Shashank Deshmukh
IPC分类号： C23F1/00 , H01L21/302
CPC分类号： H01L21/32136 , H01L21/31116
摘要： In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.
摘要翻译：在一个实施方式中，提供了能够蚀刻晶片以形成包括高k电介质层的器件的方法。该方法包括在具有低阴极温度的第一等离子体室中蚀刻上导电材料层，将晶片转移到第二室而不破坏真空，蚀刻第二室中的高k电介质层，以及从第二室转移晶片室到第一等离子体室，而不破坏真空。在第一室中以低阴极温度蚀刻下导电材料层。在一个实施方案中，高k电介质蚀刻是使用高温阴极的等离子体蚀刻。在另一个实施方案中，高k电介质蚀刻是反应离子蚀刻。

9. 发明授权

US07780862B2 Device and method for etching flash memory gate stacks comprising high-k dielectric 有权
标题翻译：用于蚀刻包括高k电介质的闪存存储器栅极堆叠的器件和方法
公开(公告)号：US07780862B2
公开(公告)日：2010-08-24
申请号：US11386054
申请日：2006-03-21
申请人： Meihua Shen , Xikun Wang , Wei Liu , Yan Du , Shashank Deshmukh
发明人： Meihua Shen , Xikun Wang , Wei Liu , Yan Du , Shashank Deshmukh
IPC分类号： H01L21/302
CPC分类号： H01L21/32136 , H01L21/31116
摘要： In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.
摘要翻译：在一个实施方式中，提供了能够蚀刻晶片以形成包括高k电介质层的器件的方法。该方法包括在具有低阴极温度的第一等离子体室中蚀刻上导电材料层，将晶片转移到第二室而不破坏真空，蚀刻第二室中的高k电介质层，以及从第二室转移晶片室到第一等离子体室，而不破坏真空。在第一室中以低阴极温度蚀刻下导电材料层。在一个实施方案中，高k电介质蚀刻是使用高温阴极的等离子体蚀刻。在另一个实施方案中，高k电介质蚀刻是反应离子蚀刻。

10. 发明申请

US20090004870A1 METHODS FOR HIGH TEMPERATURE ETCHING A HIGH-K MATERIAL GATE STRUCTURE 失效
标题翻译：高温蚀刻高K材料门结构的方法
公开(公告)号：US20090004870A1
公开(公告)日：2009-01-01
申请号：US12146303
申请日：2008-06-25
申请人： Wei Liu , Eiichi Matsusue , Meihua Shen , Shashank Deshmukh , Anh-Kiet Quang Phan , David Palagashvili , Michael D. Willwerth , Jong I. Shin , Barrett Finch , Yohei Kawase
发明人： Wei Liu , Eiichi Matsusue , Meihua Shen , Shashank Deshmukh , Anh-Kiet Quang Phan , David Palagashvili , Michael D. Willwerth , Jong I. Shin , Barrett Finch , Yohei Kawase
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01L21/28282 , H01L21/31116 , H01L21/31122 , H01L21/32137
摘要： Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.
摘要翻译：提供了在高温下蚀刻高k材料的方法。在一个实施例中，在衬底上蚀刻高k材料的方法可以包括提供其上设置有高k材料层的衬底到蚀刻室中，从包括至少含卤素气体的蚀刻气体混合物形成等离子体到蚀刻室，在蚀刻室的内部表面的温度保持超过约100摄氏度，同时在存在等离子体的同时蚀刻高k材料层，并将衬底温度保持在约100摄氏度至约250度之间摄氏度，同时在存在等离子体的同时蚀刻高k材料层。

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