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1. 发明授权

US06885235B2 Semiconductor integrated circuit device with internal power supply potential generation circuit 失效
标题翻译：具有内部电源电位生成电路的半导体集成电路器件
公开(公告)号：US06885235B2
公开(公告)日：2005-04-26
申请号：US10095080
申请日：2002-03-12
申请人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
发明人： Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Hiroaki Tanizaki , Tsukasa Ooishi
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C29/06 , G05F3/04
CPC分类号： G11C5/147
摘要： An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.
摘要翻译：内部电源电位产生电路包括连接到内部电源节点的过充电防止电路。过充电防止电路包括输出由内部电源电位确定的待确定信号的电路，放大要确定的信号之间的电位差和作为输出到节点的参考电位的差分放大电路作为信号表示应该绘制电流，并且响应于指示应当绘制电流的信号，从内部电源节点抽出电流的电流绘制电路。因此，感兴趣的半导体集成电路器件可以提供稳定的内部电源电位。

2. 发明授权

US06466509B1 Semiconductor memory device having a column select line transmitting a column select signal 失效
标题翻译：具有发送列选择信号的列选择线的半导体存储器件
公开(公告)号：US06466509B1
公开(公告)日：2002-10-15
申请号：US10050131
申请日：2002-01-18
申请人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C11/4087 , G11C2207/104
摘要： First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.
摘要翻译：第一和第二存储体设置有M个存储块，每个存储块具有第一和第二存储区域，M表示偶数个不少于两个，以及（M + 1）个读出放大器频带，其布置在每个存储块的相对侧上，并具有第一选择线和第二选择线分别用于选择第一和第二存储区，第一选择线连接到第一存储体的奇数读出放大器带和第二存储体的偶数读出放大器带第二选择线连接到第一存储体的偶数读出放大器带和第二存储体的奇数读出放大器带。

3. 发明授权

US06411560B1 Semiconductor memory device capable of reducing leakage current flowing into substrate 失效
标题翻译：能够减少流入基板的漏电流的半导体存储器件
公开(公告)号：US06411560B1
公开(公告)日：2002-06-25
申请号：US09987277
申请日：2001-11-14
申请人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Shigeki Tomishima , Mitsutaka Niiro , Masanao Maruta , Hiroshi Kato , Masatoshi Ishikawa , Takaharu Tsuji , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C514
CPC分类号： G11C7/1096 , G11C5/146 , G11C5/147 , G11C7/1078 , G11C7/22 , G11C8/10 , G11C11/4074
摘要： A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.
摘要翻译：第一电源电压被提供给读出放大器的电源节点。位线驱动器将由第二电源电压组成的列选择信号输出到GIO线路电路的N沟道MOS晶体管的栅极端子。当输入/输出数据为[1]时，低于第一电源电压的第三电源电压被提供给全局数据线。在这种情况下，利用所使用的N沟道MOS晶体管的阈值电压，建立关系：第二电源电压<=第三电源电压+阈值电压。结果，在由具有不同电压电平的多个电源电压驱动的半导体存储器件中，可以减小泄漏电流。

4. 发明授权

US06400632B1 Semiconductor device including a fuse circuit in which the electric current is cut off after blowing so as to prevent voltage fall 失效
标题翻译：包括熔断电路的半导体装置，其中在吹风之后切断电流以防止电压下降
公开(公告)号：US06400632B1
公开(公告)日：2002-06-04
申请号：US09820853
申请日：2001-03-30
申请人： Hiroaki Tanizaki , Hideto Hidaka , Tsukasa Ooishi , Shigeki Tomishima , Hiroshi Kato
发明人： Hiroaki Tanizaki , Hideto Hidaka , Tsukasa Ooishi , Shigeki Tomishima , Hiroshi Kato
IPC分类号： G11C700
CPC分类号： G11C17/16 , G11C17/18
摘要： The antifuse is brought into an electrically conducted state by setting the voltage Vpgm to a high voltage after activating the signal SA and setting the node N1 once to an L-level. By inversion of the latch, the voltage of the node N1 will be the power source voltage Vcc to bring the transistor into a non-conducted state, whereby the electric current flowing through the antifuse is cut off. A semiconductor device can be provided which includes an antifuse program circuit capable of cutting the electric current off after blowing, so as to prevent decrease in the blowing voltage.
摘要翻译：通过在激活信号SA之后将电压Vpgm设置为高电压并将节点N1设置为L电平，将反熔丝导入导电状态。通过锁存器的反相，节点N1的电压将是电源电压Vcc，以使晶体管进入非导通状态，从而切断流过反熔丝的电流。可以提供一种半导体器件，其包括能够在吹制之后切断电流的反熔丝程序电路，以防止吹送电压的降低。

5. 发明授权

US06314042B1 Fast accessible semiconductor memory device 失效
标题翻译：快速存取的半导体存储器件
公开(公告)号：US06314042B1
公开(公告)日：2001-11-06
申请号：US09181675
申请日：1998-10-29
申请人： Shigeki Tomishima , Tsukasa Ooishi , Hiroshi Kato
发明人： Shigeki Tomishima , Tsukasa Ooishi , Hiroshi Kato
IPC分类号： G11C800
CPC分类号： G11C11/4097 , G11C7/1006 , G11C8/12
摘要： A memory array is divided into a plurality of memory sub blocks in row and column directions. A column selection line is provided in the column direction in a region between blocks. A block decoding circuit generating a local column selection signal is arranged corresponding to each of the memory sub blocks. A main I/O line pair group is provided for each of the memory sub blocks and each column of the memory sub block is connected to the corresponding main I/O line pair in accordance with the local column selection line. Thus, data with a desired bit width can be produced without any increase in area occupied by the array nor decrease in the speed of column access.
摘要翻译：存储器阵列被划分成行和列方向上的多个存储器子块。在块方向之间的区域中，在列方向上设置列选择线。产生本地列选择信号的块解码电路对应于每个存储子块排列。为每个存储器子块提供主I / O线对组，并且根据本地列选择线将存储器子块的每一列连接到对应的主I / O线对。因此，可以产生具有期望比特宽度的数据，而不会增加阵列占用的面积，也不降低列访问的速度。

6. 发明授权

US6058053A Semiconductor memory device capable of high speed operation and including redundant cells 有权
标题翻译：半导体存储器件能够高速运行并且包括冗余单元
公开(公告)号：US6058053A
公开(公告)日：2000-05-02
申请号：US195212
申请日：1998-11-18
申请人： Takaharu Tsuji , Tsukasa Ooishi , Hiroshi Kato , Shigeki Tomishima , Hiroki Shimano
发明人： Takaharu Tsuji , Tsukasa Ooishi , Hiroshi Kato , Shigeki Tomishima , Hiroki Shimano
IPC分类号： G11C29/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/84 , G11C29/844
摘要： In the semiconductor memory device, independent from redundancy determination by a redundancy determining circuit, a word line activating signal (subdecode signal) for setting a word line in a normal block corresponding to a decoded address signal, is activated. A WL driver includes a driver portion for selecting a word line in the normal block, and a driver portion for selecting a spare word line in a redundant block. When redundancy is not to be used as a result of redundancy determination by the redundancy determining circuit, activated subdecode signal is inactivated. If redundancy is to be used as a result of redundancy determination, a corresponding word line is set to the selected state, using the activated subdecode signal. Thus a semiconductor memory device in which substitution can be done at high speed with high efficiency is provided.
摘要翻译：在半导体存储器件中，独立于由冗余确定电路进行的冗余确定，激活用于设置与解码的地址信号对应的正常块中的字线的字线激活信号（子代码信号）。 WL驱动器包括用于选择正常块中的字线的驱动器部分和用于在冗余块中选择备用字线的驱动器部分。作为由冗余确定电路的冗余确定的结果不使用冗余时，激活的子代码信号被去激活。如果作为冗余确定的结果使用冗余，则使用激活的子代码信号将对应的字线设置为所选择的状态。因此，提供了可以以高效率高效率地进行替换的半导体存储器件。

7. 发明授权

US06646946B2 Fast accessible semiconductor memory device 失效
公开(公告)号：US06646946B2
公开(公告)日：2003-11-11
申请号：US09976335
申请日：2001-10-15
申请人： Shigeki Tomishima , Tsukasa Ooishi , Hiroshi Kato
发明人： Shigeki Tomishima , Tsukasa Ooishi , Hiroshi Kato
IPC分类号： G11C800
CPC分类号： G11C11/4097 , G11C7/1006 , G11C8/12
摘要： A memory array is divided into a plurality of memory sub blocks in row and column directions. A column selection line is provided in the column direction in a region between blocks. A block decoding circuit generating a local column selection signal is arranged corresponding to each of the memory sub blocks. A main I/O line pair group is provided for each of the memory sub blocks and each column of the memory sub block is connected to the corresponding main I/O line pair in accordance with the local column selection line. Thus, data with a desired bit width can be produced without any increase in area occupied by the array nor decrease in the speed of column access.

8. 发明授权

US06597617B2 Semiconductor device with reduced current consumption in standby state 有权
公开(公告)号：US06597617B2
公开(公告)日：2003-07-22
申请号：US10167437
申请日：2002-06-13
申请人： Tsukasa Ooishi , Takaharu Tsuji , Masatoshi Ishikawa , Hideto Hidaka , Hiroshi Kato
发明人： Tsukasa Ooishi , Takaharu Tsuji , Masatoshi Ishikawa , Hideto Hidaka , Hiroshi Kato
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C2207/2227 , G11C2211/4067
摘要： A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

9. 发明授权

US06584005B1 Semiconductor memory device preventing erroneous writing in write operation and delay in read operation 有权
标题翻译：半导体存储器件防止写操作中的错误写入和读操作延迟
公开(公告)号：US06584005B1
公开(公告)日：2003-06-24
申请号：US10302963
申请日：2002-11-25
申请人： Hiroshi Kato , Masatoshi Ishikawa , Tsukasa Ooishi , Jun Ohtani , Hideto Hidaka
发明人： Hiroshi Kato , Masatoshi Ishikawa , Tsukasa Ooishi , Jun Ohtani , Hideto Hidaka
IPC分类号： G11C506
CPC分类号： G11C16/24 , G11C7/12 , G11C16/0475 , G11C16/0491 , G11C16/08
摘要： In write operation and read operation, a plurality of bit lines are divided into first and second bit line groups based on a selected memory cell column in a memory array. The first bit line group is connected to one of first and second voltages and the second bit line group is connected to the other voltage. Accordingly, when a word line corresponding to a selected memory cell is activated, the sources and drains of the non-selected memory cells in the selected memory cell row are set to the same voltage level. Therefore, a charging/discharging current resulting from charging and discharging of each bit line is not generated in response to activation of the word line. This prevents erroneous writing to the non-selected memory cells and delay in read operation caused by generation of the charging/discharging current.
摘要翻译：在写入操作和读取操作中，基于存储器阵列中的所选存储单元列，将多个位线分成第一位线组和第二位线组。第一位线组连接到第一和第二电压中的一个，并且第二位线组连接到另一个电压。因此，当对应于所选择的存储单元的字线被激活时，所选存储单元行中未选择的存储单元的源极和漏极被设置为相同的电压电平。因此，响应于字线的激活，不产生由每个位线的充电和放电产生的充电/放电电流。这防止了对未选择的存储单元的错误写入和由于产生充电/放电电流引起的读取操作的延迟。

10. 发明授权

US06480437B2 Semiconductor memory device permitting improved integration density and reduced accessing time 失效
标题翻译：半导体存储器件允许改进的集成密度和减少的访问时间
公开(公告)号：US06480437B2
公开(公告)日：2002-11-12
申请号：US09986584
申请日：2001-11-09
申请人： Hiroshi Kato , Tsukasa Ooishi , Hideto Hidaka
发明人： Hiroshi Kato , Tsukasa Ooishi , Hideto Hidaka
IPC分类号： G11C800
CPC分类号： G11C5/025 , G11C5/063 , G11C7/06 , G11C7/1048 , G11C7/18
摘要： A sub-amplifier includes first and second transistors which each receive the potential of a sub-I/O line pair at each gate, a third transistor controlled by a signal transmitted in the memory cell column-direction and coupling the sources of the first and second transistors and a ground potential, and fourth and fifth transistors controlled by a signal transmitted in the memory cell row-direction and coupling the drains of the first and second transistors and a main I/O line pair. Since the sub-amplifier is controlled by a signal transmitted in the column-direction, the influence of skew with a column selecting signal can be reduced.
摘要翻译：子放大器包括第一和第二晶体管，每个晶体管在每个栅极处接收子I / O线对的电位，第三晶体管由在存储器单元列方向上传输的信号控制，并且耦合第一和/ 第二晶体管和接地电位，以及由在存储单元行方向上传输的信号控制的第四和第五晶体管，并耦合第一和第二晶体管的漏极和主I / O线对。由于子放大器由在列方向上发送的信号控制，所以可以减少与列选择信号的偏斜的影响。

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