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    • 3. 发明授权
    • Measuring apparatus, measuring method, and test apparatus
    • 测量装置,测量方法和测试装置
    • US07262627B2
    • 2007-08-28
    • US11497506
    • 2006-08-01
    • Tomoyuki YamaneHirokatsu Niijima
    • Tomoyuki YamaneHirokatsu Niijima
    • G01R31/26
    • G01R29/26
    • There is provided a measuring apparatus that generates a first strobe signal and a second strobe signal in synchronization with an output signal, sequentially changes phases of the strobe signals whenever the electronic device outputs the output signal multiple times, acquires a signal level of the output signal at each phase of the strobe signals by the multiple times, counts the number of times by which the signal level of the output signal to the first strobe signal is a High level for each phase of the first strobe signal, counts the number of times by which the signal level of the output signal to the second strobe signal is a Low level for each phase of the second strobe signal, and computes a phase of a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter based on the counted number of times. The measuring apparatus measures a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter by one-time test.
    • 提供了一种与输出信号同步地产生第一选通信号和第二选通信号的测量装置,每当电子设备多次输出输出信号时,依次改变选通信号的相位,获取输出信号的信号电平 在多次选通信号的每个相位,计数第一选通信号的输出信号的信号电平对于第一选通信号的每个相位为高电平的次数,将次数计数 其中第二选通信号的输出信号的信号电平为第二选通信号的每个相位的低电平,并且计算输出信号的波形的变化点,抖动量和抖动分布的相位 基于计数次数。 测量装置通过一次性测试来测量输出信号的波形的变化点,抖动量和抖动分布。
    • 4. 发明申请
    • Test apparatus
    • 测试仪器
    • US20060129335A1
    • 2006-06-15
    • US11343463
    • 2006-01-31
    • Hirokatsu Niijima
    • Hirokatsu Niijima
    • G01B5/28G01B5/30
    • G01R31/31937G01R31/31922G01R31/31932
    • The test apparatus according to the present invention includes: a data sampler for acquiring a plurality of data sample values for data signals from the DUT; a data change point detection section for detecting a data change point from the sample value; a data change point storage section for writing the data change point based on CLK 1 and for reading the same based on CLK 2; a clock sampler for acquiring a plurality of clock sample values for clock signals from the DUT; a clock change point detection section for detecting a clock change point from the sample value; a clock change point storage section for writing the clock change point based on CLKs and reading the same based on CLK2; a phase difference detection section for detecting the phase difference between the data change point and the clock change point which are simultaneously read from the data change point storage section and the clock change point storage section; and a spec comparison section for comparing the phase difference with the spec to determine that DUT is passed or failed.
    • 根据本发明的测试装置包括:数据采样器,用于从DUT获取数据信号的多个数据采样值; 数据变化点检测部分,用于从样本值检测数据变化点; 数据改变点存储部分,用于基于CLK1写入数据变化点,并且基于CLK2读取数据变化点; 时钟采样器,用于从DUT获取时钟信号的多个时钟采样值; 时钟变化点检测部,用于从所述采样值检测时钟变化点; 时钟改变点存储部分,用于基于CLK写入时钟变化点并基于CLK2读取它; 相位差检测部分,用于检测从数据变化点存储部分和时钟变化点存储部分同时读出的数据变化点和时钟变化点之间的相位差; 以及用于将相位差与规格进行比较以确定DUT通过或失败的规格比较部分。
    • 6. 发明申请
    • CHANGING POINT DETECTING CIRCUIT, JITTER MEASURING APPARATUS AND TEST APPARATUS
    • 更换点检测电路,测径仪和测试仪
    • US20080228417A1
    • 2008-09-18
    • US11864939
    • 2007-09-29
    • TADAHIKO BABAHirokatsu Niijima
    • TADAHIKO BABAHirokatsu Niijima
    • G01R29/26G06F19/00
    • G01R31/31709G01R29/26H03K5/1534
    • A changing point detection circuit is provided that detects timing of changing points at which a logic value of a signal under measurement changes and includes a multi-strobe circuit generating a logic value data string obtained by detecting a logic value of the signal under measurement according to a plurality of strobes, each strobe having a different phase; a changing point detecting section detecting in which strobe the logic value changes based on the logic value data string; an edge designation storage section storing in advance information concerning whether an edge-type of the changing point to be detected is a rising edge or a falling edge of the signal under measurement; a selecting section selecting the changing point corresponding to the edge-type stored by the edge designation storage section from among the changing points detected by the changing point detecting section; and a strobe place storage section storing information concerning which strobe the changing point selected by the selecting section corresponds to.
    • 提供了一种改变点检测电路,其检测测量信号的逻辑值改变的点的定时,并且包括多选通电路,其产生通过根据测量信号检测被测信号的逻辑值而获得的逻辑值数据串 多个选通,每个选通具有不同的相位; 变更点检测部,根据所述逻辑值数据串检测所述逻辑值在哪个选通脉冲中变化的变化点; 边缘指定存储部分,预先存储关于被检测的切换点的边缘类型是被测信号的上升沿还是下降沿的信息; 选择部分,从由变化点检测部分检测的变化点中选择与由边缘指定存储部分存储的边缘类型对应的变化点; 以及选通存储部,其存储与所述选择部选择的所述变化点对应的选通的信息。
    • 7. 发明授权
    • Jitter measuring apparatus and a testing apparatus
    • 抖动测量仪和测试仪
    • US07002334B2
    • 2006-02-21
    • US11097102
    • 2005-04-01
    • Kouichi TanakaHirokatsu Niijima
    • Kouichi TanakaHirokatsu Niijima
    • G01R19/00H04B17/00
    • G01R31/31709G01R29/26
    • A jitter measuring apparatus for measuring jitter of an output signal output by an electronic device is provided, wherein the jitter measuring apparatus includes a multi-strobe generating unit for generating multi-strobe having more than or equal to three (3) strobes a plurality of times synchronously with the output signal output a plurality of times by the electronic device, a value detecting unit for detecting a value of the output signal for each strobe of the multi-strobe generated a plurality of times by the multi-strobe generating unit, a transition point detecting unit for detecting the position of a transition point of the value of each output signal on the basis of the value of the output signal detected by the value detecting unit, and a histogram generating unit for counting how many times the transition point detecting unit detects the transition point at every position of the transition point of the value of the output signal.
    • 提供了一种用于测量由电子设备输出的输出信号的抖动的抖动测量装置,其中所述抖动测量装置包括多选通产生单元,用于产生具有多于或等于三(3)个选通信号的多个选通 次数与电子设备输出多次的输出信号同步;值检测单元,用于检测由多选通产生单元多次产生的多选通信号的输出信号的值, 过渡点检测单元,用于根据由值检测单元检测到的输出信号的值来检测每个输出信号的值的转变点的位置;以及直方图生成单元,用于计算过渡点检测的次数 单位检测输出信号值的转换点的每个位置的转换点。
    • 8. 发明申请
    • Semiconductor test device and timing measurement method
    • 半导体测试装置及时序测量方法
    • US20050034044A1
    • 2005-02-10
    • US10936392
    • 2004-09-08
    • Hirokatsu Niijima
    • Hirokatsu Niijima
    • G01R31/317G01R31/319G01R31/3193G06F11/00G01R31/28
    • G01R31/3191G01R31/31725G01R31/31922G01R31/31937
    • A semiconductor test equipment and a timing measuring method for use in the semiconductor test equipment are provided, that can perform simultaneous measurement of timings in cycles even in a case where a capacity is large as in a test pattern for the semiconductor test equipment or a case where compared cycles are away from each other. In order to achieve this, the semiconductor test equipment includes: a data shifting flip-flip for shifting input data with a reference clock of the semiconductor test equipment by a period of one clock, provided in a secondary logical comparison circuit 71; the first logical comparison and selection circuit 71a for determining whether timings of the first defined time Ta that is a period between two pre-selected edges are good or not, and outputting a determination result; and the second logical comparison and selection circuit 71b for determining whether timings of the second defined time Tb that is a period between two pre-selected edges are good or not, and outputting a determination result.
    • 提供了半导体测试设备和用于半导体测试设备的定时测量方法,即使在半导体测试设备或壳体的测试图案中的容量大的情况下,也可以同时进行周期性测量 比较的周期彼此远离。 为了实现这一点,半导体测试设备包括:设置在辅助逻辑比较电路71中的用于将输入数据与半导体测试设备的基准时钟移位一个时钟周期的数据移位触发器; 用于确定作为两个预选边缘之间的周期的第一定义时间Ta的定时是否良好的第一逻辑比较和选择电路71a,并输出确定结果; 以及第二逻辑比较选择电路71b,用于确定作为两个预选边缘之间的周期的第二定义时间Tb的定时是否良好,并输出确定结果。
    • 10. 发明授权
    • Test apparatus and test method
    • 试验装置及试验方法
    • US07447955B2
    • 2008-11-04
    • US11290610
    • 2005-11-30
    • Hirokatsu NiijimaShinya Sato
    • Hirokatsu NiijimaShinya Sato
    • G11C29/00
    • G11C29/56
    • There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data contained in the data string read out of the memory-under-test with an expected value generated in advance, a data error counting section for counting a number of data inconsistent with the expected value, a plurality of registers, provided corresponding to each of a plurality of classes, for storing an upper limit value of a number of errors contained in the data -under-test to be classified into the class, comparing sections for comparing each of the plurality of upper limit values stored in the plurality of registers with the counted value of the data error counting section and a classifying section for classifying the memory-under-test into the class corresponding to the register storing the upper limit value which is greater than the counted value.
    • 提供了一种用于测试用于存储已经添加了纠错码的数据串的测试存储器的测试装置,具有用于比较从被测存储器中读出的数据串中包含的每个数据的逻辑比较器 具有预先产生的期望值,用于计数与期望值不一致的数据的数量的数据错误计数部分,与多个类别中的每一个对应地设置的多个寄存器,用于存储多个等级的上限值 包含在要分类到该类别的数据测试中的错误,比较将存储在多个寄存器中的多个上限值中的每一个与数据错误计数部分的计数值进行比较的部分和用于分类的分类部分 与存储上限值的寄存器对应的类别中的存储器下测试大于计数值。