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1. 发明申请

US20110107064A1 DATA PROCESSOR 有权
标题翻译：数据处理器
公开(公告)号：US20110107064A1
公开(公告)日：2011-05-05
申请号：US12915158
申请日：2010-10-29
申请人： Hiroaki NAKAYA , Yuki Kondoh , Makoto Ishikawa
发明人： Hiroaki NAKAYA , Yuki Kondoh , Makoto Ishikawa
IPC分类号： G06F9/30
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/3017 , G06F9/30185 , G06F9/3802 , G06F9/3822
摘要： The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.
摘要翻译：本发明在包括具有前缀的指令的指令集上实现有效的超标量指令问题和低功耗。采用指令取出单元，其判定指令码是否是前缀码，也可以是除了指令码以外的指令码，并输出确定结果和16位指令码。与此同时，基于确定结果解码指令代码的解码器和分别解码前缀码的解码器分别设置。此外，在固定长度指令代码（如16位修改）之前，将前缀提供给每个解码器。与前缀码相邻的固定长度指令代码被提供给与前缀码的解码器相同的流水线的每个解码器。

2. 发明授权

US08924689B2 Semiconductor device with instruction code and prefix code predecoders 有权
标题翻译：具有指令码和前缀码预解码器的半导体器件
公开(公告)号：US08924689B2
公开(公告)日：2014-12-30
申请号：US12915158
申请日：2010-10-29
申请人： Hiroaki Nakaya , Yuki Kondoh , Makoto Ishikawa
发明人： Hiroaki Nakaya , Yuki Kondoh , Makoto Ishikawa
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/3017 , G06F9/30185 , G06F9/3802 , G06F9/3822
摘要： The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.
摘要翻译：本发明在包括具有前缀的指令的指令集上实现有效的超标量指令问题和低功耗。采用指令取出单元，其判定指令码是否是前缀码，也可以是除了指令码以外的指令码，并输出确定结果和16位指令码。与此同时，基于确定结果解码指令代码的解码器和分别解码前缀码的解码器分别设置。此外，在固定长度指令代码（如16位修改）之前，将前缀提供给每个解码器。与前缀码相邻的固定长度指令代码被提供给与前缀码的解码器相同的流水线的每个解码器。

3. 发明授权

US07356649B2 Semiconductor data processor 有权
标题翻译：半导体数据处理器
公开(公告)号：US07356649B2
公开(公告)日：2008-04-08
申请号：US10520653
申请日：2002-09-30
申请人： Yuki Kondoh , Tatsuya Kamei , Makoto Ishikawa
发明人： Yuki Kondoh , Tatsuya Kamei , Makoto Ishikawa
IPC分类号： G06F12/00
CPC分类号： G06F12/0888
摘要： A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.
摘要翻译：半导体数据处理器具有构成高速缓冲存储器的第一存储器（6），能够由第一存储器构成可高速缓存区域或不可缓存区域的第二存储器（20），以及能够执行当第二存储器被读取访问作为不可缓存区域时，用于输出与读访问相对应的数据的操作。用于第二存储器的可缓存区域和不可缓存区域的指定由第二存储器映射到的存储器空间的可缓存区域或不可缓存区域的指定来确定。该指定可以在数据处理器的操作模式下执行，或者例如设置控制寄存器。

4. 发明申请

US20050257011A1 Semiconductor data processor 有权
标题翻译：半导体数据处理器
公开(公告)号：US20050257011A1
公开(公告)日：2005-11-17
申请号：US10520653
申请日：2002-09-30
申请人： Yuki Kondoh , Tatsuya Kamei , Makoto Ishikawa
发明人： Yuki Kondoh , Tatsuya Kamei , Makoto Ishikawa
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0888
摘要： A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.
摘要翻译：半导体数据处理器具有构成高速缓冲存储器的第一存储器（6），能够由第一存储器构成可高速缓存区域或不可缓存区域的第二存储器（20），以及能够执行当第二存储器被读取访问作为不可缓存区域时，用于输出与读访问相对应的数据的操作。用于第二存储器的可缓存区域和不可缓存区域的指定由第二存储器映射到的存储器空间的可缓存区域或不可缓存区域的指定来确定。该指定可以在数据处理器的操作模式下执行，或者例如设置控制寄存器。

5. 发明申请

US20060034452A1 Code calculating device 审中-公开
标题翻译：代码计算设备
公开(公告)号：US20060034452A1
公开(公告)日：2006-02-16
申请号：US10518481
申请日：2002-06-20
申请人： Motonobu Tonomura , Yuki Kondoh
发明人： Motonobu Tonomura , Yuki Kondoh
IPC分类号： H04L9/00
CPC分类号： H04L9/304 , G06F7/724 , G06F7/725 , H03M13/15 , H04L1/0061 , H04L9/3066 , H04L2209/12
摘要： A code computing apparatus with an error detection code (CRC) generating function and an elliptic curve cryptography (ECC) function, comprising a matrix element computation part 30 for generating matrix elements from parameter values set in first and second registers 201 and 202, a matrix element register 51 for holding the matrix elements generated by the matrix element computation part, and an inner product calculation part 40 for executing inner product calculation between the matrix elements held by the matrix element register and data set in a third register. The matrix element computation part selectively generates matrix elements for error detection and matrix elements for encryption by changing the parameters to be set in the first and second registers, and the inner product calculation part is shared to error control code generation and data encryption by altering the matrix elements to be held in the matrix element register.
摘要翻译：具有错误检测码（CRC）生成函数和椭圆曲线密码（ECC）函数的代码计算装置，包括用于从在第一和第二寄存器201和202中设置的参数值生成矩阵元素的矩阵元素计算部分30，矩阵用于保持由矩阵元素计算部分生成的矩阵元素的元素寄存器51，以及用于执行由矩阵元素寄存器保持的矩阵元素与第三寄存器中设置的数据之间的内积计算的内积计算部40。矩阵元素计算部通过改变要设置在第一和第二寄存器中的参数来选择性地生成用于错误检测的矩阵元素和用于加密的矩阵元素，并且通过改变内部乘积计算部分来进行错误控制代码生成和数据加密要保存在矩阵元素寄存器中的矩阵元素。

6. 发明授权

US08813070B2 Data processor with interfaces for peripheral devices 有权
标题翻译：具有外围设备接口的数据处理器
公开(公告)号：US08813070B2
公开(公告)日：2014-08-19
申请号：US12958687
申请日：2010-12-02
申请人： Tohru Nojiri , Yuki Kondoh
发明人： Tohru Nojiri , Yuki Kondoh
IPC分类号： G06F9/455 , G06F13/10
CPC分类号： G06F9/45533 , G06F9/4411 , G06F9/45541 , G06F13/102 , G06F13/105
摘要： This invention is intended to reduce the hypervisor overhead. In the data processor disclosed herein, when a device driver calls for access to a control register to activate a process of a dedicated controlled peripheral device, the access is handled directly without intervention of processing by the hypervisor. When an interrupt is generated from a dedicated controlled peripheral device, a process is directly initiated by the device driver of the operating system governing the peripheral device without intervention of processing by the hypervisor. By implementing this manner of control in the processor, it becomes possible to carry out peripheral device control without intervention of processing by the hypervisor. Thereby, the hypervisor overhead is alleviated.
摘要翻译：本发明旨在减少管理程序开销。在本文公开的数据处理器中，当设备驱动程序要求访问控制寄存器以激活专用受控外围设备的处理时，直接处理访问，而不用管理程序进行处理。当从专用的受控外围设备产生中断时，由管理外围设备的操作系统的设备驱动程序直接发起一个过程，而不会由管理程序进行处理。通过在处理器中实现这种控制方式，可以在不经管理程序处理的情况下执行外围设备控制。从而减轻虚拟机管理程序开销。

7. 发明授权

US08713563B2 Data processor with virtual machine management 有权
标题翻译：具有虚拟机管理的数据处理器
公开(公告)号：US08713563B2
公开(公告)日：2014-04-29
申请号：US11869565
申请日：2007-10-09
申请人： Yuki Kondoh , Takashi Matsumoto , Keisuke Toyama , Toru Nojiri
发明人： Yuki Kondoh , Takashi Matsumoto , Keisuke Toyama , Toru Nojiri
IPC分类号： G06F9/455
CPC分类号： G06F9/5077 , G06F9/45558 , G06F2009/45583
摘要： A data processor includes: a central processing unit (CPU), in which a plurality of virtual machines (101), each running an application program under controls of different operating systems, and a virtual machine manager (190) for controlling the plurality of virtual machines are selectively arranged according to information set in mode registers (140, 150, 151); and a resource access management module (110) for managing access to hardware resource available for the plurality of virtual machines. The resource access management module accepts, as inputs, the information set in the mode registers and access control information of the central processing unit to the hardware resource, compares the information thus input with information set in a control register, and controls whether or not to permit access to the hardware resource in response to the access control information. As a result, redesign involved in changes in system specifications can be reduced, and a malfunction owing to resource contention can be prevented. The invention contributes to increase of security.
摘要翻译：数据处理器包括：中央处理单元（CPU），其中在不同操作系统的控制下运行应用程序的多个虚拟机（101）和用于控制多个虚拟机的虚拟机器管理器（190）根据在模式寄存器（140,150,151）中设置的信息来选择性地布置机器; 以及用于管理对可用于所述多个虚拟机的硬件资源的访问的资源访问管理模块（110）。资源访问管理模块将在模式寄存器中设置的信息和中央处理单元的访问控制信息作为输入接受到硬件资源，将由此输入的信息与设置在控制寄存器中的信息进行比较，并且控制是否响应于访问控制信息允许访问硬件资源。因此，可以减少涉及系统规格变化的重新设计，并且可以防止由于资源争用引起的故障。本发明有助于提高安全性。

8. 发明授权

US07454594B2 Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements 有权
标题翻译：用于通过SIMD算术单元实现软件流水线的处理器，在多个离散元件上同时处理每个SIMD指令
公开(公告)号：US07454594B2
公开(公告)日：2008-11-18
申请号：US10320615
申请日：2002-12-17
申请人： Yuki Kondoh
发明人： Yuki Kondoh
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30109
摘要： A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and permit software pipelining between arithmetic operations performed in parallel by a SIMD arithmetic unit. A selector for adding an operation for interchanging multiple outputs of a SIMD arithmetic unit is added to a data path. A register file is divided in accordance with the output bit fields of the SIMD arithmetic unit. A means of specifying multiple registers as a SIMD instruction's output operand is added. Therefore, part of the output results of arithmetic operations performed in parallel by the SIMD arithmetic unit can be stored in a register providing the input for another arithmetic operation. Software pipelining is rendered achievable in this manner.
摘要翻译：公开了一种处理器及其算术指令处理方法和算术运算控制方法，其向SIMD算术指令添加新的操作数指定选项，并允许由SIMD算术单元并行执行的算术运算之间的软件流水线化。添加用于将SIMD运算单元的多个输出进行交换的操作的选择器被添加到数据路径。寄存器文件根据SIMD算术单元的输出位字段进行划分。添加了将多个寄存器指定为SIMD指令的输出操作数的方法。因此，通过SIMD算术单元并行执行的算术运算的输出结果的一部分可以存储在提供另一算术运算的输入的寄存器中。软件流水线可以以这种方式实现。

9. 发明授权

US07003651B2 Program counter (PC) relative addressing mode with fast displacement 失效
公开(公告)号：US07003651B2
公开(公告)日：2006-02-21
申请号：US10017198
申请日：2001-12-18
申请人： Yuki Kondoh , Osamu Nishii
发明人： Yuki Kondoh , Osamu Nishii
IPC分类号： G06F9/32
CPC分类号： G06F9/382 , G06F9/322 , G06F9/324 , G06F9/3802
摘要： The invention allows the execution of a PC relative branch instruction with displacement is speeded up without changing the instruction operations of existing processors and without requiring new instructions. The branch target address calculation is made faster by calculating the lower portion of the branch target address prior to storing the instruction word in a cache or buffer, and writing the calculation result into the displacement field of the instruction word and into a bit that has been added to the cache or the buffer, such that some calculation is executed simultaneously to be skipped later at the time of execution of the instruction by using the executed calculation result stored in the cache or buffer.

10. 发明授权

US09798679B2 Information processing device and processor 有权
公开(公告)号：US09798679B2
公开(公告)日：2017-10-24
申请号：US12892645
申请日：2010-09-28
申请人： Yuki Kondoh
发明人： Yuki Kondoh
IPC分类号： G06F12/02 , G06F12/14
CPC分类号： G06F12/1441 , G06F12/1425
摘要： A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.

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