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1. 发明申请

US20120250399A1 MEMORY CIRCUIT USING SPIN MOSFETS, PATH TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, SWITCHING BOX CIRCUIT, SWITCHING BLOCK CIRCUIT, AND FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：使用旋转MOSFET的存储器电路，具有存储器功能的路径晶体管电路，开关盒电路，开关块电路和现场可编程门阵列
公开(公告)号：US20120250399A1
公开(公告)日：2012-10-04
申请号：US13403308
申请日：2012-02-23
申请人： Hideyuki SUGIYAMA , Masato ODA , Shinobu FUJITA , Tetsufumi TANAMOTO , Mizue ISHIKAWA , Takao MARUKAME , Tomoaki INOKUCHI , Yoshiaki SAITO
发明人： Hideyuki SUGIYAMA , Masato ODA , Shinobu FUJITA , Tetsufumi TANAMOTO , Mizue ISHIKAWA , Takao MARUKAME , Tomoaki INOKUCHI , Yoshiaki SAITO
IPC分类号： G11C11/16 , H03K19/177
CPC分类号： G11C5/148 , G11C11/161 , G11C11/1673 , G11C11/1675
摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.
摘要翻译：根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

2. 发明申请

US20110194342A1 NONVOLATILE MEMORY CIRCUIT USING SPIN MOS TRANSISTORS 有权
标题翻译：使用旋转MOS晶体管的非易失性存储器电路
公开(公告)号：US20110194342A1
公开(公告)日：2011-08-11
申请号：US12889881
申请日：2010-09-24
申请人： Hideyuki SUGIYAMA , Tetsufumi TANAMOTO , Takao MARUKAME , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO
发明人： Hideyuki SUGIYAMA , Tetsufumi TANAMOTO , Takao MARUKAME , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO
IPC分类号： G11C11/14
CPC分类号： G11C14/0081
摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
摘要翻译：某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

3. 发明申请

US20090179667A1 RECONFIGURABLE LOGIC CIRCUIT 有权
标题翻译：可重新配置的逻辑电路
公开(公告)号：US20090179667A1
公开(公告)日：2009-07-16
申请号：US12339638
申请日：2008-12-19
申请人： Hideyuki SUGIYAMA , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO , Tetsufumi TANAMOTO
发明人： Hideyuki SUGIYAMA , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO , Tetsufumi TANAMOTO
IPC分类号： H03K19/094 , H03K19/173
CPC分类号： H03K19/1733 , G11C11/161 , G11C11/1675 , G11C11/1697
摘要： It is made possible to provide a reconfigurable logic circuit with which high integration can be achieved. A reconfigurable logic circuit includes: a multiplexer which includes a plurality of spin MOSFETs each having a source and drain containing a magnetic material, and a selecting portion including a plurality of MOSFETs and selecting a spin MOSFET from the plurality of spin MOSFETs, based on control data transmitted from control lines; a determining circuit which determines whether magnetization of the magnetic material of the source and drain of a selected spin MOSFET, which is selected by the selecting portion, is in a first state or in a second state; and a first and second write circuits which put the magnetization of the magnetic material of the source and drain of the selected spin MOSFET into the second and first states respectively by supplying a write current flowing between the source and drain of the selected spin MOSFET.
摘要翻译：可以提供可实现高集成度的可重构逻辑电路。可重配置逻辑电路包括：多路复用器，其包括多个自旋MOSFET，每个具有包含磁性材料的源极和漏极，以及包括多个MOSFET的选择部分，并且基于控制从多个自旋MOSFET中选择自旋MOSFET 从控制线传输的数据; 确定电路，其确定由选择部分选择的所选择的自旋MOSFET的源极和漏极的磁性材料的磁化是处于第一状态还是处于第二状态; 以及第一和第二写入电路，其通过提供在选定的自旋MOSFET的源极和漏极之间流动的写入电流，将所选自旋MOSFET的源极和漏极的磁性材料的磁化分别置于第二和第一状态。

4. 发明申请

US20100072529A1 STACK HAVING HEUSLER ALLOY, MAGNETORESISTIVE ELEMENT AND SPIN TRANSISTOR USING THE STACK, AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有合金的堆叠，使用堆叠的磁体元件和旋转晶体管及其制造方法
公开(公告)号：US20100072529A1
公开(公告)日：2010-03-25
申请号：US12565303
申请日：2009-09-23
申请人： Takao MARUKAME , Mizue ISHIKAWA , Tomoaki INOKUCHI , Hideyuki SUGIYAMA , Yoshiaki SAITO
发明人： Takao MARUKAME , Mizue ISHIKAWA , Tomoaki INOKUCHI , Hideyuki SUGIYAMA , Yoshiaki SAITO
IPC分类号： H01L29/82 , B05D3/02 , B32B15/04
CPC分类号： H01L29/66984 , H01F10/1936 , H01F10/265 , H01L27/228 , H01L43/10 , H01L43/12 , Y10T428/12611
摘要： A stack includes a crystalline MgO layer, crystalline Heusler alloy layer, and amorphous Heusler alloy layer. The crystalline Heusler alloy layer is provided on the MgO layer. The amorphous Heusler alloy layer is provided on the crystalline Heusler alloy layer.
摘要翻译：堆叠包括结晶MgO层，结晶Heusler合金层和非晶Heusler合金层。结晶Heusler合金层设置在MgO层上。非晶Heusler合金层设置在结晶Heusler合金层上。

5. 发明申请

US20090180215A1 TUNNELING MAGNETORESISTIVE EFFECT ELEMENT AND SPIN MOS FIELD-EFFECT TRANSISTOR 有权
标题翻译：隧道磁场效应元件和旋转MOS场效应晶体管
公开(公告)号：US20090180215A1
公开(公告)日：2009-07-16
申请号：US12342383
申请日：2008-12-23
申请人： Mizue ISHIKAWA , Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi
发明人： Mizue ISHIKAWA , Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi
IPC分类号： G11B5/33
CPC分类号： G11B5/3909 , B82Y10/00 , B82Y25/00 , G01R33/098 , G11B5/3906 , G11C11/161 , G11C11/1659 , H01F10/1936 , H01F10/3254 , H01F10/3295 , H01L27/228 , H01L29/66984 , H01L43/08 , H01L43/10
摘要： A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.
摘要翻译：磁阻效应元件包括第一铁磁层，Cr层，Heusler合金层，阻挡层和第二铁磁层。第一铁磁层具有体心立方晶格结构。 Cr层形成在第一铁磁层上并具有体心立方晶格结构。 Heusler合金层形成在Cr层上。阻挡层形成在Heusler合金层上。第二铁磁层形成在阻挡层上。

6. 发明申请

US20120218802A1 CONTENT ADDRESSABLE MEMORY 失效
标题翻译：内容可寻址内存
公开(公告)号：US20120218802A1
公开(公告)日：2012-08-30
申请号：US13403398
申请日：2012-02-23
申请人： Takao MARUKAME , Tomoaki INOKUCHI , Hideyuki SUGIYAMA , Mizue ISHIKAWA , Yoshiaki SAITO , Atsuhiro KINOSHITA , Kosuke TATSUMURA
发明人： Takao MARUKAME , Tomoaki INOKUCHI , Hideyuki SUGIYAMA , Mizue ISHIKAWA , Yoshiaki SAITO , Atsuhiro KINOSHITA , Kosuke TATSUMURA
IPC分类号： G11C15/02
CPC分类号： G11C15/02 , G11C11/161 , G11C15/046 , H01L27/228
摘要： One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.
摘要翻译：一个实施例提供一种内容可寻址存储器，包括：一对自旋MOSFET，其包括：第一自旋MOSFET，其磁化状态根据存储的数据设置; 以及第二自旋MOSFET，其磁化状态根据存储的数据设定，第二自旋MOSFET与第一自旋MOSFET并联连接; 第一布线，被配置为施加栅极电压，使得第一自旋MOSFET和第二自旋MOSFET中的任何一个根据搜索数据变为导电; 以及配置为向第一自旋MOSFET和第二自旋MOSFET两者施加电流的第二布线。

7. 发明申请

US20090050948A1 SPIN MOS FIELD EFFECT TRANSISTOR AND TUNNELING MAGNETORESISTIVE EFFECT ELEMENT USING STACK HAVING HEUSLER ALLOY 有权
标题翻译：旋转磁场效应晶体管和隧道电磁效应元件使用具有合金的堆叠
公开(公告)号：US20090050948A1
公开(公告)日：2009-02-26
申请号：US12194797
申请日：2008-08-20
申请人： Mizue ISHIKAWA , Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi
发明人： Mizue ISHIKAWA , Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi
IPC分类号： H01L29/82 , G11B5/33
CPC分类号： G11B5/3909 , B82Y10/00 , B82Y25/00 , G11B5/3929 , G11C11/161 , G11C11/1659 , H01L27/228 , H01L29/66984 , H01L43/08
摘要： A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer.
摘要翻译：自旋MOS场效应晶体管包括源电极和漏电极，每个源极和漏极具有通过层叠杂质扩散层，（001）取向的MgO层和Heusler合金而获得的结构。杂质扩散层形成在半导体层的表面区域中。（001）取向的MgO层形成在杂质扩散层上。 Heusler合金形成在MgO层上。

8. 发明申请

US20120273856A1 TUNNELING MAGNETORESISTIVE EFFECT ELEMENT AND SPIN MOS FIELD-EFFECT 有权
标题翻译：隧道磁场效应元件和旋转MOS场效应晶体管
公开(公告)号：US20120273856A1
公开(公告)日：2012-11-01
申请号：US13533198
申请日：2012-06-26
申请人： Mizue ISHIKAWA , Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi
发明人： Mizue ISHIKAWA , Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi
IPC分类号： H01L29/82
CPC分类号： G11B5/3909 , B82Y10/00 , B82Y25/00 , G01R33/098 , G11B5/3906 , G11C11/161 , G11C11/1659 , H01F10/1936 , H01F10/3254 , H01F10/3295 , H01L27/228 , H01L29/66984 , H01L43/08 , H01L43/10
摘要： A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.
摘要翻译：磁阻效应元件包括第一铁磁层，Cr层，Heusler合金层，阻挡层和第二铁磁层。第一铁磁层具有体心立方晶格结构。 Cr层形成在第一铁磁层上并具有体心立方晶格结构。 Heusler合金层形成在Cr层上。阻挡层形成在Heusler合金层上。第二铁磁层形成在阻挡层上。

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