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1. 发明授权

US07157749B2 Bipolar transistor with a GaAs substrate and a SiGe base or collector 失效
标题翻译：具有GaAs衬底和SiGe基极或集电极的双极晶体管
公开(公告)号：US07157749B2
公开(公告)日：2007-01-02
申请号：US11053548
申请日：2005-02-09
申请人： Hidetoshi Fujimoto , Tetsuro Nozu , Yoshitomo Sagae , Akira Yoshioka
发明人： Hidetoshi Fujimoto , Tetsuro Nozu , Yoshitomo Sagae , Akira Yoshioka
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/267 , H01L29/1004 , H01L29/7371
摘要： A bipolar transistor is provided which includes a GaAs substrate, an n-type collector region formed on the GaAs substrate, a p-type base region formed on the n-type collector region and having a p-type base layer of SiGe having a composition lattice-matched with the GaAs substrate, and an n-type emitter region formed on the p-type base region. A bipolar transistor may include a GaAs substrate, a collector region of a first conductivity type formed on the GaAs substrate and including a collector contact layer of the first conductivity type SiGe, which has a composition lattice-matched with the GaAs substrate, a base region of a second conductivity type formed on the collector region of the first conductivity type, and an emitter region of the first conductivity type formed on the base region of the second conductivity type.
摘要翻译：提供一种双极晶体管，其包括GaAs衬底，形成在GaAs衬底上的n型集电极区域，形成在n型集电极区域上并具有具有组成的SiGe的p型基极层的p型基极区域与GaAs衬底晶格匹配，以及形成在p型基极区上的n型发射极区。双极晶体管可以包括GaAs衬底，在GaAs衬底上形成的第一导电类型的集电极区域，并且包括具有与GaAs衬底晶格匹配的组成的第一导电类型SiGe的集电极接触层，形成在第一导电类型的集电极区域上的第二导电类型的第一导电类型的发射极区域和形成在第二导电类型的基极区域上的第一导电类型的发射极区域。

2. 发明申请

US20050189565A1 Bipolar transistor and method of manufacturing the same 失效
标题翻译：双极晶体管及其制造方法
公开(公告)号：US20050189565A1
公开(公告)日：2005-09-01
申请号：US11053548
申请日：2005-02-09
申请人： Hidetoshi Fujimoto , Tetsuro Nozu , Yoshitomo Sagae , Akira Yoshioka
发明人： Hidetoshi Fujimoto , Tetsuro Nozu , Yoshitomo Sagae , Akira Yoshioka
IPC分类号： H01L21/331 , H01L29/10 , H01L29/22 , H01L29/267 , H01L29/737
CPC分类号： H01L29/267 , H01L29/1004 , H01L29/7371
摘要： A bipolar transistor is provided which includes a GaAs substrate, an n-type collector region formed on the GaAs substrate, a p-type base region formed on the n-type collector region and having a p-type base layer of SiGe having a composition lattice-matched with the GaAs substrate, and an n-type emitter region formed on the p-type base region. A bipolar transistor may include a GaAs substrate, a collector region of a first conductivity type formed on the GaAs substrate and including a collector contact layer of the first conductivity type SiGe, which has a composition lattice-matched with the GaAs substrate, a base region of a second conductivity type formed on the collector region of the first conductivity type, and an emitter region of the first conductivity type formed on the base region of the second conductivity type.
摘要翻译：提供一种双极晶体管，其包括GaAs衬底，形成在GaAs衬底上的n型集电极区域，形成在n型集电极区域上并具有具有组成的SiGe的p型基极层的p型基极区域与GaAs衬底晶格匹配，以及形成在p型基极区上的n型发射极区。双极晶体管可以包括GaAs衬底，在GaAs衬底上形成的第一导电类型的集电极区域，并且包括具有与GaAs衬底晶格匹配的组成的第一导电类型SiGe的集电极接触层，形成在第一导电类型的集电极区域上的第二导电类型的第一导电类型的发射极区域和形成在第二导电类型的基极区域上的第一导电类型的发射极区域。

3. 发明授权

US06756615B2 Heterojunction bipolar transistor and its manufacturing method 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US06756615B2
公开(公告)日：2004-06-29
申请号：US10407428
申请日：2003-04-07
申请人： Akira Yoshioka , Tetsuro Nozu
发明人： Akira Yoshioka , Tetsuro Nozu
IPC分类号： H01L310328
CPC分类号： H01L29/66318 , H01L29/0817 , H01L29/7371
摘要： A heterojunction bipolar transistor comprises, an emitter made of a first compound semiconductor of a first conductivity type; a base made of a second compound semiconductor of a second conductivity type and having a bandgap smaller than the first compound semiconductor; and a collector made of a third compound semiconductor of a first conductivity type and having a bandgap wider than the second compound semiconductor. The emitter and the base form a heterojunction of type I. The base and the collector form a heterojunction of type II. Further, the base includes impurities by a concentration equal to or more than 5×1019 cm−3.
摘要翻译：异质结双极晶体管包括由第一导电类型的第一化合物半导体制成的发射极; 由第二导电类型的第二化合物半导体制成并具有小于第一化合物半导体的带隙的基底; 以及由第一导电类型的第三化合物半导体制成的并且具有比第二化合物半导体宽的带隙的集电极。发射极和基极形成I型的异质结。基极和集电极形成II型的异质结。此外，碱包括等于或大于5×10 -9 cm -3的浓度的杂质。

4. 发明授权

US08541834B2 Semiconductor device and method for manufacturing same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08541834B2
公开(公告)日：2013-09-24
申请号：US13238605
申请日：2011-09-21
申请人： Tetsuro Nozu
发明人： Tetsuro Nozu
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/404 , H01L29/407 , H01L29/42368 , H01L29/512 , H01L29/66734 , H01L29/7397 , H01L29/8725
摘要： According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a control electrode, a first main electrode, an internal electrode, and an insulating region. The control electrode is provided inside a trench. The first main electrode is in conduction with the third semiconductor region. The internal electrode is provided in the trench and in conduction with the first main electrode. The insulating region is provided between an inner wall of the trench and the internal electrode. The internal electrode includes a first internal electrode part included in a first region of the trench and a second internal electrode part included in a second region between the first region and the first main electrode. A spacing between the first internal electrode part and the inner wall is wider than a spacing between the second internal electrode part and the inner wall.
摘要翻译：根据一个实施例，半导体器件包括第一半导体区域，第二半导体区域，第三半导体区域，控制电极，第一主电极，内部电极和绝缘区域。控制电极设置在沟槽内。第一主电极与第三半导体区域导通。内部电极设置在沟槽中并与第一主电极导通。绝缘区域设置在沟槽的内壁和内部电极之间。内部电极包括包括在沟槽的第一区域中的第一内部电极部分和包括在第一区域和第一主要电极之间的第二区域中的第二内部电极部分。第一内部电极部分和内壁之间的间隔比第二内部电极部分和内壁之间的间隔宽。

5. 发明申请

US20050275114A1 Semiconductor device and semiconductor apparatus 失效
标题翻译：半导体装置及半导体装置
公开(公告)号：US20050275114A1
公开(公告)日：2005-12-15
申请号：US10975385
申请日：2004-10-29
申请人： Tetsuro Nozu
发明人： Tetsuro Nozu
IPC分类号： H01L21/52 , H01L23/13 , H01L23/367 , H01L29/06 , H01L29/74
CPC分类号： H01L24/32 , H01L23/13 , H01L23/367 , H01L24/29 , H01L24/48 , H01L24/83 , H01L29/0657 , H01L2224/05644 , H01L2224/27013 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83051 , H01L2224/83192 , H01L2224/83365 , H01L2224/8385 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/10158 , H01L2924/10329 , H01L2924/1305 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2924/01031 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device comprises a bonding surface to be mounted with adhesive or solder on a mounting surface of a mounting member. One or more grooves are provided on the bonding surface that extend in a direction substantially parallel to one side surface of the semiconductor device.
摘要翻译：一种半导体器件包括在安装构件的安装表面上安装有粘合剂或焊料的接合表面。一个或多个凹槽设置在接合表面上，该凹槽沿着基本上平行于半导体器件的一个侧表面的方向延伸。

6. 发明授权

US08330184B2 Bidirectional voltage-regulator diode 有权
标题翻译：双向稳压二极管
公开(公告)号：US08330184B2
公开(公告)日：2012-12-11
申请号：US13050231
申请日：2011-03-17
申请人： Tetsuro Nozu
发明人： Tetsuro Nozu
IPC分类号： H01L29/66
CPC分类号： H01L29/861 , H01L29/6609 , H01L29/66098 , H01L29/732
摘要： In one embodiment, a bidirectional voltage-regulator diode includes first to fifth semiconductor layers formed on an inner surface of a first recess formed in a semiconductor substrate of an N-type in the order. The first semiconductor layer of the N-type has a first impurity concentration lower than an impurity concentration of the semiconductor substrate. The second semiconductor layer of a P-type has a second impurity concentration. The third semiconductor layer of the P-type has a third impurity concentration higher than the second impurity concentration. The fourth semiconductor layer of the P-type has a fourth impurity concentration lower than the third impurity concentration. The fifth semiconductor layer of the N-type has a fifth impurity concentration.
摘要翻译：在一个实施例中，双向电压调节二极管包括依次形成在形成在N型半导体衬底中的第一凹部的内表面上的第一至第五半导体层。 N型的第一半导体层具有比半导体衬底的杂质浓度低的第一杂质浓度。 P型的第二半导体层具有第二杂质浓度。 P型的第三半导体层具有比第二杂质浓度高的第三杂质浓度。 P型的第四半导体层具有比第三杂质浓度低的第四杂质浓度。 N型的第五半导体层具有第五杂质浓度。

7. 发明申请

US20100127259A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100127259A1
公开(公告)日：2010-05-27
申请号：US12558474
申请日：2009-09-11
申请人： Tetsuro Nozu
发明人： Tetsuro Nozu
IPC分类号： H01L27/06 , H01L29/04
CPC分类号： H01L27/0629 , H01L27/0255
摘要： A semiconductor device has a MOS transistor that has a gate connected to a first terminal, a source connected to a second terminal and a drain connected to a third terminal, a first polysilicon diode that has an anode connected to the first terminal, a first single-crystalline silicon diode that is connected to a cathode of the first polysilicon diode at a cathode thereof and to the second terminal at an anode thereof, has a reverse breakdown voltage lower than a reverse breakdown voltage of the first polysilicon diode, a second polysilicon diode that has a cathode connected to the first terminal and a second single-crystalline silicon diode that is connected to an anode of the second polysilicon diode at an anode thereof and to the third terminal at a cathode thereof, has a reverse breakdown voltage lower than a reverse breakdown voltage of the second polysilicon.
摘要翻译：半导体器件具有MOS晶体管，其具有连接到第一端子的栅极，连接到第二端子的源极和连接到第三端子的漏极，具有连接到第一端子的阳极的第一多晶硅二极管，第一单极在其阴极处连接到第一多晶硅二极管的阴极和在其阳极处连接到第二端子的晶体硅二极管具有低于第一多晶硅二极管的反向击穿电压的反向击穿电压，第二多晶硅二极管其具有连接到第一端子的阴极和在其阳极处连接到第二多晶硅二极管的阳极的第二单晶硅二极管和其阴极处的第三端子的反向击穿电压低于第二多晶硅的反向击穿电压。

8. 发明授权

US07038250B2 Semiconductor device suited for a high frequency amplifier 失效
标题翻译：适用于高频放大器的半导体器件
公开(公告)号：US07038250B2
公开(公告)日：2006-05-02
申请号：US10834347
申请日：2004-04-29
申请人： Toru Sugiyama , Tetsuro Nozu , Kouhei Morizuka
发明人： Toru Sugiyama , Tetsuro Nozu , Kouhei Morizuka
IPC分类号： H01L29/732 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/1004 , H01L29/0817 , H01L29/7371
摘要： According to the present invention, there is a provided a semiconductor device having, a collector contact layer made of an n-type GaAs layer; a first collector layer formed on the collector contact layer and made of an n-type GaAs layer; a second collector layer formed on the first collector layer and made of a p-type GaAs layer; a third collector layer formed on the second collector layer and made of an n-type InGaP layer; a fourth collector layer formed on the third collector layer and made of an n-type InGaP layer having an impurity concentration higher than that of the third collector layer; a fifth collector layer formed on the fourth collector layer and made of an n-type GaAs layer; a base layer formed on the fifth collector layer and made of a p-type GaAs layer; and an emitter layer formed on the base layer and made of an n-type InGaP layer.
摘要翻译：根据本发明，提供了一种具有由n型GaAs层制成的集电极接触层的半导体器件; 形成在集电极接触层上并由n型GaAs层构成的第一集电极层; 第二集电体层，形成在第一集电层上，由p型GaAs层构成; 形成在第二集电体层上并由n型InGaP层制成的第三集电极层; 第三集电体层，形成在第三集电体层上，由具有比第三集电体层的杂质浓度高的n型InGaP层构成; 形成在第四集电体层上并由n型GaAs层制成的第五集电极层; 基底层，形成在第五集电体层上，由p型GaAs层构成; 以及形成在基底层上并由n型InGaP层制成的发射极层。

9. 发明授权

US5387808A Heterojunction bipolar transistors with sloped regions 失效
标题翻译：具有倾斜区域的异质结双极晶体管
公开(公告)号：US5387808A
公开(公告)日：1995-02-07
申请号：US006758
申请日：1993-01-21
申请人： Tetsuro Nozu
发明人： Tetsuro Nozu
IPC分类号： H01L29/205 , H01L21/331 , H01L27/06 , H01L29/73 , H01L29/737 , H01L27/102
CPC分类号： H01L27/0605 , H01L29/737
摘要： The present invention is directed toward a heterojunction bipolar transistor integrated circuit in which the collector layers of two heterojunction bipolar transistors are provided on a semi-insulating substrate. The collector layers have at least one surface that is sloped relative to the substrate. Base layers are provided on the sloped portions a common emitter layer is provided in contact with the base layers. Alternatively, the common emitter layer is provided on the substrate and etched to form to sloped surface thereon. Base and collector layers are then formed on the sloped surfaces of the common emitter layer.
摘要翻译：本发明涉及一种异质结双极晶体管集成电路，其中两个异质结双极晶体管的集电极层设置在半绝缘衬底上。集电体层具有相对于衬底倾斜的至少一个表面。基底层设置在倾斜部分上，与底层接触地提供公共发射极层。或者，公共发射极层设置在衬底上并被蚀刻以形成其上的倾斜表面。然后在公共发射极层的倾斜表面上形成基极和集电极层。

10. 发明授权

US5332912A Heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管
公开(公告)号：US5332912A
公开(公告)日：1994-07-26
申请号：US51617
申请日：1993-04-23
申请人： Tetsuro Nozu , Norio Iizuka , Junko Akagi , Torakiti Kobayashi , Masao Obara
发明人： Tetsuro Nozu , Norio Iizuka , Junko Akagi , Torakiti Kobayashi , Masao Obara
IPC分类号： H01L29/205 , H01L21/331 , H01L29/73 , H01L29/737 , H01L29/61
CPC分类号： H01L29/7371
摘要： A heterojunction bipolar transistor comprises n.sup.+ -type GaAs collector contact region, an n-type GaAs collector region, a p.sup.+ -type GaAs base region, an n-type AlGaAs emitter region, and an n.sup.+ -type InGaAs emitter contact region, all of which are formed on a semiinsulative GaAs substrate. A heterojunction is formed by the base region and the emitter region. The emitter region is formed in mesa shape by dry etching. Around this mesa, B.sup.+ ion-implanted high-resistance region is formed. The base-emitter Junction is isolated from the ion-implanted region. The heterojunction bipolar transistor therefore has little on-voltage changes.
摘要翻译：异质结双极晶体管包括n +型GaAs集电极接触区域，n型GaAs集电极区域，p +型GaAs基极区域，n型AlGaAs发射极区域和n +型InGaAs发射极接触区域，所有这些形成在半绝缘GaAs衬底上。由基极区域和发射极区域形成异质结。发射极区域通过干蚀刻形成为台面形状。围绕该台面形成B +离子注入高电阻区域。基极 - 发射极结与离子注入区隔离。因此异质结双极晶体管具有很小的导通电压变化。

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