专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06819607B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06819607B2
公开(公告)日：2004-11-16
申请号：US10360863
申请日：2003-02-10
申请人： Hideo Mukai , Kaoru Nakagawa
发明人： Hideo Mukai , Kaoru Nakagawa
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/81
摘要： In a DRAM semiconductor memory device, a DRAM semiconductor memory device disclosed herein comprises a first spare element SWL provided for each of a plurality of normal banks BANK0-BANK15 formed by dividing a memory cell array into a plurality of sections, a second spare element SWL provided for a spare bank BANKSP different from the normal banks, a plurality of first spare decoders SRD0-SRD3 for selectively operating the first spare element, a plurality of second spare decoders SRD0-SRD3 for selectivedly operating the second spare element, and a substitution-control circuits FS0a-FS27a, RWLON1-RWLON2, SRDact0-SRDact3 for selectively assigning the second spare elements to arbitrary banks of the plurality of normal banks. With the above structure, the total number of the spare elements of the defective memory cells of the DRAM can be reduced while the relieving ratio is being maintained. As a result, the area efficiency of the redundant circuit on the chip can be improved.
摘要翻译：在DRAM半导体存储器件中，本文公开的DRAM半导体存储器件包括：通过将存储单元阵列划分为多个部分而形成的多个正常库BANK0-BANK15中的每一个设置的第一备用元件SWL，第二备用元件SWL 提供了与正常库不同的备用库BANKSP，用于选择性地操作第一备用元件的多个第一备用解码器SRD0-SRD3，用于选择性地操作第二备用元件的多个第二备用解码器SRD0-SRD3，控制电路FS0a-FS27a，RWLON1-RWLON2，SRDact0-SRDact3，用于选择性地将第二备用元件分配给多个正常库中的任意组。利用上述结构，可以减小DRAM的有缺陷的存储单元的备用元件的总数，同时保持释放比。结果，能够提高芯片上的冗余电路的面积效率。

2. 发明授权

US06567322B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06567322B1
公开(公告)日：2003-05-20
申请号：US09528177
申请日：2000-03-17
申请人： Hideo Mukai , Kaoru Nakagawa
发明人： Hideo Mukai , Kaoru Nakagawa
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C29/81
摘要： In a DRAM semiconductor memory device, a DRAM semiconductor memory device disclosed herein comprises a first spare element SWL provided for each of a plurality of normal banks BANK0-BANK15 formed by dividing a memory cell array into a plurality of sections, a second spare element SWL provided for a spare bank BANKSP different from the normal banks, a plurality of first spare decoders SRD0-SRD3 for selectively operating the first spare element, a plurality of second spare decoders SRD0-SRD3 for selectively operating the second spare element, and a substitution-control circuits FS0a-FS27a, RWLON1-RWLON2, SRDact0-SRDact3 for selectively assigning the second spare elements to arbitrary banks of the plurality of normal banks. With the above structure, the total number of the spare elements of the defective memory cells of the DRAM can be reduced while the relieving ratio is being maintained. As a result, the area efficiency of the redundant circuit on the chip can be improved.
摘要翻译：在DRAM半导体存储器件中，本文公开的DRAM半导体存储器件包括：通过将存储单元阵列划分为多个部分而形成的多个正常库BANK0-BANK15中的每一个设置的第一备用元件SWL，第二备用元件SWL 提供了与正常库不同的备用银行BANKSP，用于选择性地操作第一备用元件的多个第一备用解码器SRD0-SRD3，用于选择性地操作第二备用元件的多个第二备用解码器SRD0-SRD3，控制电路FS0a-FS27a，RWLON1-RWLON2，SRDact0-SRDact3，用于选择性地将第二备用元件分配给多个正常库中的任意组。利用上述结构，可以减小DRAM的有缺陷的存储单元的备用元件的总数，同时保持释放比。结果，能够提高芯片上的冗余电路的面积效率。

3. 发明授权

US08315110B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US08315110B2
公开(公告)日：2012-11-20
申请号：US13315967
申请日：2011-12-09
申请人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C7/10
摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

4. 发明授权

US08228733B2 Three-dimensionally stacked nonvolatile semiconductor memory 有权
标题翻译：三维堆叠的非易失性半导体存储器
公开(公告)号：US08228733B2
公开(公告)日：2012-07-24
申请号：US13164938
申请日：2011-06-21
申请人： Naoya Tokiwa , Hideo Mukai
发明人： Naoya Tokiwa , Hideo Mukai
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/30 , G11C29/028 , G11C2029/1202 , H01L27/11578 , H01L27/11582
摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.
摘要翻译：本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元，具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于对应于地址信号的字线。

5. 发明申请

US20090230434A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090230434A1
公开(公告)日：2009-09-17
申请号：US12402758
申请日：2009-03-12
申请人： Tsuneo Inaba , Hideo Mukai
发明人： Tsuneo Inaba , Hideo Mukai
IPC分类号： H01L29/66
CPC分类号： H01L27/101 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/71 , H01L27/0688 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/147
摘要： A semiconductor memory device comprises a semiconductor substrate; a memory block formed on the semiconductor substrate and including plural stacked cell array layers of cell arrays each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contacts extending in the stack direction of the cell array layers and connecting the first lines in the cell arrays with diffusion regions formed on the semiconductor substrate. A certain one of the cell array layers is smaller in the number of the first lines divided and the number of contacts connected than the cell array layers in a lower layer located closer to the semiconductor substrate than the certain one.
摘要翻译：半导体存储器件包括半导体衬底; 存储块，其形成在所述半导体基板上，并且包括多个单元阵列层叠单元阵列层，每个单元阵列层包括多条第一线，与所述多条第一线交叉的多条第二线，以及连接在所述第一线与第二线的交点处的存储单元两条线之间以及在单元阵列层的堆叠方向上延伸的多个触点，并且将形成在半导体基板上的扩散区域连接在单元阵列中的第一线。单元阵列层中的某一个在分隔的第一线数目和连接的半导体衬底的下层中的单元阵列层的数量比特定的数量小。

6. 发明申请

US20090219750A1 NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开
标题翻译：非易失性存储器件及其控制方法
公开(公告)号：US20090219750A1
公开(公告)日：2009-09-03
申请号：US12394487
申请日：2009-02-27
申请人： Naoya TOKIWA , Hiroshi Maejima , Hideo Mukai
发明人： Naoya TOKIWA , Hiroshi Maejima , Hideo Mukai
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C17/12 , G11C5/02 , G11C8/08 , G11C8/14 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0092 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a line selector circuit operative to decode an address signal to select the first and second lines; and a control circuit operative to execute control on at least one of data erase, write and read for the memory cell connected between the first and second lines selected at the line selector circuit. The control circuit executes control based on one parameter selected among a plurality of parameters. The line selector circuit specifies the parameter based on a first address portion in the address signal and selects the first and second lines based on a second address portion in the address signal.
摘要翻译：非易失性存储器件包括存储单元阵列，其包括第一和第二相交线以及布置在第一和第二线的交点处的电可擦除可编程存储单元，每个存储单元包含可变电阻元件; 行选择器电路，用于解码地址信号以选择第一和第二行; 以及控制电路，用于对连接在线选择器电路中选择的第一和第二线之间的存储单元的数据擦除，写入和读取中的至少一个执行控制。控制电路基于从多个参数中选择的一个参数来执行控制。线选择器电路基于地址信号中的第一地址部分来指定参数，并且基于地址信号中的第二地址部分选择第一和第二行。

7. 发明授权

US4769676A Image forming apparatus including means for removing residual toner 失效
标题翻译：图像形成装置包括用于去除残留调色剂的装置
公开(公告)号：US4769676A
公开(公告)日：1988-09-06
申请号：US20715
申请日：1987-03-02
申请人： Hideo Mukai , Takashi Shimazaki , Goro Oda
发明人： Hideo Mukai , Takashi Shimazaki , Goro Oda
IPC分类号： G03G21/00
CPC分类号： G03G21/0058 , G03G21/0064 , G03G2221/0005
摘要： An image forming apparatus comprises an image carrier, a main charger for charging the image carrier, an exposure unit for exposing the image carrier to form a latent image thereon, developing unit for developing the latent image to form a developed image on the image carrier with a developing agent, the developing unit is provided so that there is a gap between it and the image carrier, and a transferring charger for transferring the developed image onto a sheet-like material. A bias voltage is applied across the developing unit and image carrier to cause the developing agent to transfer from the developing unit to the latent image via the gap, and to cause the residual developing agent remaining on the image carrier after the developed image transferring by the transferring charger to transfer to the developing unit via the gap.
摘要翻译：图像形成装置包括图像载体，用于对图像载体进行充电的主充电器，用于曝光图像载体以在其上形成潜像的曝光单元，用于使潜像显影以在图像载体上形成显影图像的显影单元，显影剂，显影单元被设置成使得其与图像载体之间存在间隙，以及用于将显影图像转印到片状材料上的转印充电器。跨越显影单元和图像载体施加偏置电压，使得显影剂经由间隙从显影单元转移到潜像，并且在显影图像转印之后使剩余的显影剂残留在图像载体上转移充电器通过间隙转移到显影单元。

8. 发明授权

US4748472A Developing apparatus with multiple blade developer conditioner 失效
标题翻译：具有多叶片显影剂调理剂的显影装置
公开(公告)号：US4748472A
公开(公告)日：1988-05-31
申请号：US14776
申请日：1987-02-13
申请人： Hideo Mukai , Tomoyuki Asada
发明人： Hideo Mukai , Tomoyuki Asada
IPC分类号： G03G15/08 , G03G15/00
CPC分类号： G03G15/0812
摘要： In a developing apparatus for developing an electrostatic latent image by applying a charged developer to the latent image formed on the surface of an image carrier, a housing, stored with the developer, is provided with a developing roller for feeding the developer therefrom to a developing position. A plurality of blades are pressed against the developing roller, whereby the developer is triboelectrically charged.
摘要翻译：在通过将电荷显影剂施加到形成在图像载体的表面上的潜像来显影静电潜像的显影装置中，与显影剂一起存储的壳体设置有用于将显影剂从显影剂供给到显影剂位置。多个叶片被压靠在显影辊上，由此显影剂被摩擦带电。

9. 发明授权

US4371252A Contact type charging device with pliable contact member 失效
标题翻译：接触式充电装置，具有柔软的接触构件
公开(公告)号：US4371252A
公开(公告)日：1983-02-01
申请号：US241113
申请日：1981-03-06
申请人： Kohachi Uchida , Yoshitsugu Nakatomi , Toshimasa Takano , Hideo Mukai
发明人： Kohachi Uchida , Yoshitsugu Nakatomi , Toshimasa Takano , Hideo Mukai
IPC分类号： G03G15/02
CPC分类号： G03G15/0216
摘要： A charging device includes a piled cloth contact which is formed of pliable material, has an electric resistance chosen to be 10.sup.8 .OMEGA..multidot.cm and contacts a photosensitive layer of a photosensitive drum. An electrode is connected to the contact and has a lower electric resistance than that of the contact. A D.C. power source and A.C. power source supply D.C. and A.C. voltages on the electrode to charge the photosensitive layer.
摘要翻译：充电装置包括由柔韧材料形成的堆叠布接触，其电阻选择为108欧姆x厘米，并与感光鼓的感光层接触。电极连接到触点，并具有比触点低的电阻。 D.C.电源和A.C.电源D.C.和A.C.电压在电极上对感光层充电。

10. 发明授权

US4055313A Apparatus for exchanging rewound rolls in a roll slitting and rewinding machine 失效
标题翻译：用于在卷筒分切复卷机中交换卷绕辊的装置
公开(公告)号：US4055313A
公开(公告)日：1977-10-25
申请号：US597402
申请日：1975-07-18
申请人： Toshiaki Yamaguchi , Keizo Narita , Hideo Mukai
发明人： Toshiaki Yamaguchi , Keizo Narita , Hideo Mukai
IPC分类号： B65H19/22 , B65H35/02
CPC分类号： B65H19/2284 , B65H35/02 , B65H2301/4148
摘要： A roll slitting and rewinding machine apparatus for exchanging rewound rolls comprises a frame holding a plurality of slitted strip rewinding roll supporting means arranged in two rows and a carrier rotatably supporting said frame so that said frame is movable from a vertically arranged position and a horizontally arranged position. The carrier being movable from a forward position to a retracted position, whereby when said carrier takes said forward position with said frame taking said first position the rewinding rolls are in condition of rewinding operation while when said carrier takes said retracted position with said frame taking said second position the rewinding rolls are removed from their respective support means.
摘要翻译：一种用于交换卷绕辊的卷筒卷绕和重绕机装置包括：一个框架，其保持多个布置成两排的带状卷绕卷筒支承装置和一个可旋转地支撑所述框架的托架，从而所述框架可从垂直布置的位置移动，位置。所述托架可从前进位置移动到缩回位置，由此当所述托架在所述框架处于所述第一位置时将所述前端位置移动时，所述收卷辊处于重绕操作的状态，同时当所述托架采取所述缩回位置时，第二位置，将卷绕辊从它们各自的支撑装置移除。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式