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1. 发明授权

US08228733B2 Three-dimensionally stacked nonvolatile semiconductor memory 有权
标题翻译：三维堆叠的非易失性半导体存储器
公开(公告)号：US08228733B2
公开(公告)日：2012-07-24
申请号：US13164938
申请日：2011-06-21
申请人： Naoya Tokiwa , Hideo Mukai
发明人： Naoya Tokiwa , Hideo Mukai
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/30 , G11C29/028 , G11C2029/1202 , H01L27/11578 , H01L27/11582
摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.
摘要翻译：本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元，具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于对应于地址信号的字线。

2. 发明申请

US20090219750A1 NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开
标题翻译：非易失性存储器件及其控制方法
公开(公告)号：US20090219750A1
公开(公告)日：2009-09-03
申请号：US12394487
申请日：2009-02-27
申请人： Naoya TOKIWA , Hiroshi Maejima , Hideo Mukai
发明人： Naoya TOKIWA , Hiroshi Maejima , Hideo Mukai
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C17/12 , G11C5/02 , G11C8/08 , G11C8/14 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0092 , G11C2213/31 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a line selector circuit operative to decode an address signal to select the first and second lines; and a control circuit operative to execute control on at least one of data erase, write and read for the memory cell connected between the first and second lines selected at the line selector circuit. The control circuit executes control based on one parameter selected among a plurality of parameters. The line selector circuit specifies the parameter based on a first address portion in the address signal and selects the first and second lines based on a second address portion in the address signal.
摘要翻译：非易失性存储器件包括存储单元阵列，其包括第一和第二相交线以及布置在第一和第二线的交点处的电可擦除可编程存储单元，每个存储单元包含可变电阻元件; 行选择器电路，用于解码地址信号以选择第一和第二行; 以及控制电路，用于对连接在线选择器电路中选择的第一和第二线之间的存储单元的数据擦除，写入和读取中的至少一个执行控制。控制电路基于从多个参数中选择的一个参数来执行控制。线选择器电路基于地址信号中的第一地址部分来指定参数，并且基于地址信号中的第二地址部分选择第一和第二行。

3. 发明授权

US07800935B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07800935B2
公开(公告)日：2010-09-21
申请号：US12252675
申请日：2008-10-16
申请人： Hiroshi Maejima , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
发明人： Hiroshi Maejima , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
IPC分类号： G11C11/00
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2211/5642 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.
摘要翻译：一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 ＆Dgr; R2的关系。

4. 发明申请

US20090237979A1 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US20090237979A1
公开(公告)日：2009-09-24
申请号：US12408232
申请日：2009-03-20
申请人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
IPC分类号： G11C11/00 , G11C7/22
CPC分类号： G11C8/10 , G11C7/18 , G11C7/22 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0076 , G11C2207/2263 , G11C2211/5647 , G11C2213/31 , G11C2213/56 , G11C2213/72
摘要： A semiconduct or memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.
摘要翻译：半导体或存储器件包括存储单元阵列，其包括布置在字线和位线的交点处的多个存储单元; 读/写电路，用于执行对存储器单元的数据读/写; 以及操作电路，用于将来自多个存储器单元的读/写电路读出的某些长度数据与要写入多个存储器单元的一定长度数据进行比较，并作出决定，并创建表示决定结果的标志。读/写电路根据该标志反转要写入存储单元的一定长度数据中的每个位，并且仅写入特定长度数据和标志的重写预期数据。读/写电路读取与其对应的标志一定的长度数据，并根据该标志反转一定长度数据中的每一位。

5. 发明申请

US20110249498A1 THREE-DIMENSIONALLY STACKED NONVOLATILE SEMICONDUTOR MEMORY 有权
标题翻译：三维堆叠非易失性半导体存储器
公开(公告)号：US20110249498A1
公开(公告)日：2011-10-13
申请号：US13164938
申请日：2011-06-21
申请人： Naoya TOKIWA , Hideo Mukai
发明人： Naoya TOKIWA , Hideo Mukai
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/30 , G11C29/028 , G11C2029/1202 , H01L27/11578 , H01L27/11582
摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.
摘要翻译：本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元，具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于对应于地址信号的字线。

6. 发明授权

US07983084B2 Three-dimensionally stacked nonvolatile semiconductor memory 有权
标题翻译：三维堆叠的非易失性半导体存储器
公开(公告)号：US07983084B2
公开(公告)日：2011-07-19
申请号：US12553266
申请日：2009-09-03
申请人： Naoya Tokiwa , Hideo Mukai
发明人： Naoya Tokiwa , Hideo Mukai
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/30 , G11C29/028 , G11C2029/1202 , H01L27/11578 , H01L27/11582
摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.
摘要翻译：本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元，具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于对应于地址信号的字线。

7. 发明申请

US20100097858A1 THREE-DIMENSIONALLY STACKED NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：三维堆叠非易失性半导体存储器
公开(公告)号：US20100097858A1
公开(公告)日：2010-04-22
申请号：US12553266
申请日：2009-09-03
申请人： Naoya Tokiwa , Hideo Mukai
发明人： Naoya Tokiwa , Hideo Mukai
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/30 , G11C29/028 , G11C2029/1202 , H01L27/11578 , H01L27/11582
摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.
摘要翻译：本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元，具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于对应于地址信号的字线。

8. 发明授权

US07876626B2 Semiconductor memory device and semiconductor memory system 有权
标题翻译：半导体存储器件和半导体存储器系统
公开(公告)号：US07876626B2
公开(公告)日：2011-01-25
申请号：US12408232
申请日：2009-03-20
申请人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Satoru Takase , Naoya Tokiwa , Katsuaki Isobe
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C7/18 , G11C7/22 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/0069 , G11C2013/0076 , G11C2207/2263 , G11C2211/5647 , G11C2213/31 , G11C2213/56 , G11C2213/72
摘要： A semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag.
摘要翻译：半导体存储器件包括存储单元阵列，其包括布置在字线和位线的交点处的多个存储单元; 读/写电路，用于执行对存储器单元的数据读/写; 以及操作电路，用于将来自多个存储器单元的读/写电路读出的某些长度数据与要写入多个存储器单元的一定长度数据进行比较，并作出决定，并创建表示决定结果的标志。读/写电路根据该标志反转要写入存储单元的一定长度数据中的每个位，并且仅写入特定长度数据和标志的重写预期数据。读/写电路读取与其对应的标志一定的长度数据，并根据该标志反转一定长度数据中的每一位。

9. 发明申请

US20090109728A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20090109728A1
公开(公告)日：2009-04-30
申请号：US12252675
申请日：2008-10-16
申请人： Hiroshi MAEJIMA , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
发明人： Hiroshi MAEJIMA , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2211/5642 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.
摘要翻译：一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 DeltaR2的关系。

10. 发明授权

US08315110B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US08315110B2
公开(公告)日：2012-11-20
申请号：US13315967
申请日：2011-12-09
申请人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C7/10
摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

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