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1. 发明申请

US20090033427A1 OSCILLATOR, PLL OSCILLATOR, RADIO APPARATUS 审中-公开
标题翻译：振荡器，PLL振荡器，无线电设备
公开(公告)号：US20090033427A1
公开(公告)日：2009-02-05
申请号：US12246871
申请日：2008-10-07
申请人： Akihide Sai , Hidenori Okuni , Takafumi Yamaji
发明人： Akihide Sai , Hidenori Okuni , Takafumi Yamaji
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/0891 , H03L7/18
摘要： An oscillator includes a plurality of oscillating units connected in parallel with each other, and a control unit which controls the number of parallel connections of the plurality of oscillating units based on an instruction signal indicating accuracy to be tolerated with respect to oscillation outputs of the oscillating units.
摘要翻译：振荡器包括彼此并联连接的多个振荡单元，以及控制单元，其基于指示信号来控制多个振荡单元的并联数量，所述指令信号指示相对于振荡器的振荡输出允许的精度单位。

2. 发明申请

US20070182493A1 OSCILLATOR, PLL OSCILLATOR, RADIO APPARATUS 失效
标题翻译：振荡器，PLL振荡器，无线电设备
公开(公告)号：US20070182493A1
公开(公告)日：2007-08-09
申请号：US11532630
申请日：2006-09-18
申请人： Akihide Sai , Hidenori Okuni , Takafumi Yamaji
发明人： Akihide Sai , Hidenori Okuni , Takafumi Yamaji
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/0891 , H03L7/18
摘要： An oscillator includes a plurality of oscillating units connected in parallel with each other, and a control unit which controls the number of parallel connections of the plurality of oscillating units based on an instruction signal indicating accuracy to be tolerated with respect to oscillation outputs of the oscillating units.
摘要翻译：振荡器包括彼此并联连接的多个振荡单元，以及控制单元，其基于指示信号来控制多个振荡单元的并联数量，所述指令信号指示相对于振荡器的振荡输出允许的精度单位。

3. 发明授权

US08461887B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US08461887B2
公开(公告)日：2013-06-11
申请号：US13409770
申请日：2012-03-01
申请人： Hidenori Okuni , Akihide Sai
发明人： Hidenori Okuni , Akihide Sai
IPC分类号： H03L7/06
CPC分类号： H03L7/0891 , H03L7/18
摘要： There is provided an integrated circuit in which a reference-signal source generates a reference signal having a basic frequency, a phase locked loop includes a voltage-controlled oscillator, a first frequency divider to generate a first frequency-divided signal based on the signal by N, a phase detector, a charge pump and a loop filter, the second frequency generates a second frequency-divided signal based on the signal generated by the voltage-controlled oscillator by M, wherein a minimum absolute value of a difference between the basic frequency multiplied by “K” and a frequency of the second frequency-divided signal is equal to or less than a low cutoff frequency of a bandpass filter or equal to or higher than a high cutoff frequency of the bandpass filter, the bandpass filter being represented by a transfer function from an input of the voltage-controlled oscillator to an output of the phase locked loop.
摘要翻译：提供了一种集成电路，其中参考信号源产生具有基本频率的参考信号，锁相环包括压控振荡器，第一分频器，以基于该信号产生第一分频信号 N，相位检测器，电荷泵和环路滤波器，第二频率基于由压控振荡器产生的信号由M产生第二分频信号，其中基本频率之间的差的最小绝对值乘以“K”，并且第二分频信号的频率等于或小于带通滤波器的低截止频率或等于或高于带通滤波器的高截止频率，带通滤波器由从压控振荡器的输入到锁相环的输出的传递函数。

4. 发明授权

US07449961B2 Parallel controlled connections of the plurality of ring oscillator units, PLL, radio apparatus 失效
标题翻译：多个环形振荡器单元，PLL，无线电设备的并行控制连接
公开(公告)号：US07449961B2
公开(公告)日：2008-11-11
申请号：US11532630
申请日：2006-09-18
申请人： Akihide Sai , Hidenori Okuni , Takafumi Yamaji
发明人： Akihide Sai , Hidenori Okuni , Takafumi Yamaji
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/0891 , H03L7/18
摘要： An oscillator includes a plurality of oscillating units connected in parallel with each other, and a control unit which controls the number of parallel connections of the plurality of oscillating units based on an instruction signal indicating accuracy to be tolerated with respect to oscillation outputs of the oscillating units.
摘要翻译：振荡器包括彼此并联连接的多个振荡单元，以及控制单元，其基于指示信号来控制多个振荡单元的并联数量，所述指令信号指示相对于振荡器的振荡输出允许的精度单位。

5. 发明授权

US08831153B2 Quadrature error compensating circuit 有权
标题翻译：正交误差补偿电路
公开(公告)号：US08831153B2
公开(公告)日：2014-09-09
申请号：US13724277
申请日：2012-12-21
申请人： Hidenori Okuni , Junya Matsuno , Hideo Kasami , Tsuyoshi Kogawa
发明人： Hidenori Okuni , Junya Matsuno , Hideo Kasami , Tsuyoshi Kogawa
IPC分类号： H03D1/00 , H04L27/06 , H04L27/38
CPC分类号： H04L27/38 , H04L27/3863
摘要： According to one embodiment, a quadrature error compensating circuit for acquiring an in-phase component signal and a quadrature component signal, includes a first filter, a first multiplier, a first subtractor, a second filter, a correlation calculating circuit. The first multiplier multiplies the in-phase component signal by a control value. The correlation calculating circuit calculates a cross-correlation value between an output of the first filter and an output of the second filter, and uses the cross-correlation value as the control value.
摘要翻译：根据一个实施例，用于获取同相分量信号和正交分量信号的正交误差补偿电路包括第一滤波器，第一乘法器，第一减法器，第二滤波器，相关计算电路。第一乘法器将同相分量信号乘以控制值。相关计算电路计算第一滤波器的输出和第二滤波器的输出之间的互相关值，并使用互相关值作为控制值。

6. 发明授权

US07778358B2 Receiver, wireless device and method for cancelling a DC offset component 失效
标题翻译：接收机，无线设备和消除DC偏移分量的方法
公开(公告)号：US07778358B2
公开(公告)日：2010-08-17
申请号：US11851851
申请日：2007-09-07
申请人： Hidenori Okuni , Rui Ito , Hiroshi Yoshida
发明人： Hidenori Okuni , Rui Ito , Hiroshi Yoshida
IPC分类号： H04L25/06 , H04L25/10
CPC分类号： H04L25/06
摘要： A receiver includes a memory for storing DC offset amounts generated by an analog circuit; an amplifier; a DC offset amount generator for generating a first offset value and a second offset value to be removed from the received signal amplified at the amplifier; a first DC offset component-removing unit for removing the first DC offset value from the received signal before the amplifier; a second DC offset component-removing unit for removing the second DC offset value from the received signal after the amplifier; and an updating unit for updating the DC offset amount stored in the memory in view of the second DC offset value generated by the DC offset amount generator. A maximum value of the second DC offset value is set larger than a multiplication value of a gain of the amplifier by a minimum resolution value of the first DC offset value.
摘要翻译：接收机包括用于存储由模拟电路产生的DC偏移量的存储器; 放大器 DC偏移量发生器，用于产生从放大器放大的接收信号中去除的第一偏移值和第二偏移值; 第一DC偏移分量去除单元，用于从放大器之前的接收信号中去除第一DC偏移值; 第二DC偏移分量去除单元，用于从放大器之后的接收信号中去除第二DC偏移值; 以及更新单元，用于根据由DC偏移量产生器生成的第二DC偏移值来更新存储在存储器中的DC偏移量。将第二DC偏移值的最大值设定为大于放大器的增益乘以第一DC偏移值的最小分辨率值。

7. 发明申请

US20080181334A1 RECEIVER, WIRELESS DEVICE AND METHOD FOR CANCELLING A DC OFFSET COMPONENT 失效
标题翻译：接收器，无线设备和用于取消直流偏移分量的方法
公开(公告)号：US20080181334A1
公开(公告)日：2008-07-31
申请号：US11851680
申请日：2007-09-07
申请人： Hidenori Okuni , Rui Ito , Hiroshi Yoshida
发明人： Hidenori Okuni , Rui Ito , Hiroshi Yoshida
IPC分类号： H04L25/10 , H03K5/007
CPC分类号： H04L25/06 , H03M1/1019 , H03M1/12
摘要： A receiver includes a memory for storing DC offset amounts in accordance with a DC offset component remaining in a received signal; a first DC offset component-removing unit configured so as to generate a first DC offset amount from the DC offset amounts stored in the memory and to remove the first DC offset amount from the received signal; an amplifier for amplifying a signal output from the first DC offset component-removing unit; and a second DC offset component-removing unit configured so as to generate a second DC offset amount from the DC offset amounts stored in the memory in view of a gain of the amplifier and remove the second DC offset amount from the signal amplified by the amplifier.
摘要翻译：接收机包括用于根据接收信号中剩余的DC偏移分量存储DC偏移量的存储器; 第一DC偏移分量去除单元，被配置为从存储在存储器中的DC偏移量产生第一DC偏移量，并从接收信号中去除第一DC偏移量; 放大器，用于放大从第一DC偏移分量去除单元输出的信号; 以及第二DC偏移分量去除单元，被配置为从放大器的增益的视角考虑存储在存储器中的DC偏移量产生第二DC偏移量，并且从由放大器放大的信号中去除第二DC偏移量。

8. 发明授权

US07764748B2 Receiver, wireless device and method for cancelling a DC offset component 失效
标题翻译：接收机，无线设备和消除DC偏移分量的方法
公开(公告)号：US07764748B2
公开(公告)日：2010-07-27
申请号：US11851680
申请日：2007-09-07
申请人： Hidenori Okuni , Rui Ito , Hiroshi Yoshida
发明人： Hidenori Okuni , Rui Ito , Hiroshi Yoshida
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L25/06 , H03M1/1019 , H03M1/12
摘要： A receiver includes a memory for storing DC offset amounts in accordance with a DC offset component remaining in a received signal; a first DC offset component-removing unit configured so as to generate a first DC offset amount from the DC offset amounts stored in the memory and to remove the first DC offset amount from the received signal; an amplifier for amplifying a signal output from the first DC offset component-removing unit; and a second DC offset component-removing unit configured so as to generate a second DC offset amount from the DC offset amounts stored in the memory in view of a gain of the amplifier and remove the second DC offset amount from the signal amplified by the amplifier.
摘要翻译：接收机包括用于根据接收信号中剩余的DC偏移分量存储DC偏移量的存储器; 第一DC偏移分量去除单元，被配置为从存储在存储器中的DC偏移量产生第一DC偏移量，并从接收信号中去除第一DC偏移量; 放大器，用于放大从第一DC偏移分量去除单元输出的信号; 以及第二DC偏移分量去除单元，被配置为从放大器的增益的视角考虑存储在存储器中的DC偏移量产生第二DC偏移量，并且从由放大器放大的信号中去除第二DC偏移量。

9. 发明申请

US20090219186A1 FILTER CIRCUIT, RECEIVER USING THE SAME, AND FILTERING METHOD USING THE SAME 审中-公开
标题翻译：过滤器电路，使用它的接收器和使用其的滤波方法
公开(公告)号：US20090219186A1
公开(公告)日：2009-09-03
申请号：US12366712
申请日：2009-02-06
申请人： Hiroaki Ishihara , Masahiro Hosoya , Hidenori Okuni
发明人： Hiroaki Ishihara , Masahiro Hosoya , Hidenori Okuni
IPC分类号： H03M1/12
CPC分类号： H04B1/12
摘要： According to an aspect of the present invention, there is provided a filter circuit including: an ADC that converts a first analog signal into a first digital signal; a digital filter that extracts an interference component from the first digital signal and generates a second digital signal; a DAC that converts the second digital signal into a second analog signal; a delayer that delays the first analog signal based on a delay caused in the second analog signal and generates a delayed first analog signal; a subtractor that subtracts the second analog signal from the delayed first analog signal and generates an output signal; and a controller that controls the digital filter based on a remaining interference component that is remaining in the output signal.
摘要翻译：根据本发明的一个方面，提供了一种滤波电路，包括：将第一模拟信号转换为第一数字信号的ADC; 数字滤波器，从所述第一数字信号中提取干扰分量并产生第二数字信号; DAC，其将所述第二数字信号转换为第二模拟信号; 延迟器，其基于在所述第二模拟信号中引起的延迟来延迟所述第一模拟信号，并产生延迟的第一模拟信号; 减法器，从延迟的第一模拟信号中减去第二模拟信号并产生输出信号; 以及控制器，其基于剩余在所述输出信号中的剩余干扰分量来控制所述数字滤波器。

10. 发明申请

US20090067555A1 FILTER CIRCUIT, RECEIVER USING THE SAME AND FILTERING METHOD 审中-公开
标题翻译：滤波电路，使用它的接收器和滤波方法
公开(公告)号：US20090067555A1
公开(公告)日：2009-03-12
申请号：US12203745
申请日：2008-09-03
申请人： Masahiro HOSOYA , Toshiya Mitomo , Hidenori Okuni , Hiroaki Ishihara , Osamu Watanabe
发明人： Masahiro HOSOYA , Toshiya Mitomo , Hidenori Okuni , Hiroaki Ishihara , Osamu Watanabe
IPC分类号： H04L27/06 , H03M1/00 , H03M3/00
CPC分类号： H03H15/00 , G11C27/024
摘要： A filter circuit includes a sampler which samples an input signal to generate a first analog signal, an analog-to-digital converter which converts the first analog signal into a first digital signal, a digital filter which extracts a signal component out of a desired band from the first digital signal to generate a second digital signal, a digital-to-analog converter which converts the second digital signal into a second analog signal, a delay device which imparts a signal delay to the first analog signal to supply a third analog signal, the signal delay being equal to a delay time of the second analog signal relative to the first analog signal, and a subtracter which subtracts the second analog signal from the third analog signal to generate an output signal.
摘要翻译：滤波器电路包括对输入信号进行采样以产生第一模拟信号的采样器，将第一模拟信号转换为第一数字信号的模数转换器，从期望频带中提取信号分量的数字滤波器从所述第一数字信号产生第二数字信号，数模转换器，其将所述第二数字信号转换为第二模拟信号;延迟装置，其向所述第一模拟信号施加信号延迟以提供第三模拟信号信号延迟等于第二模拟信号相对于第一模拟信号的延迟时间;以及减法器，其从第三模拟信号中减去第二模拟信号以产生输出信号。

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