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1. 发明授权

US08209849B2 Method for producing multilayer inductor 有权
标题翻译：多层电感器的制造方法
公开(公告)号：US08209849B2
公开(公告)日：2012-07-03
申请号：US12549903
申请日：2009-08-28
申请人： Hidekazu Sato , Masazumi Arata , Kunio Oda , Yoshimitsu Satoh
发明人： Hidekazu Sato , Masazumi Arata , Kunio Oda , Yoshimitsu Satoh
IPC分类号： H01F7/06
CPC分类号： H01F17/0013 , H01F3/14 , H01F17/04 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49163 , Y10T29/49169 , Y10T156/10
摘要： A method of A production method including interdiffusion of a Ni component in a magnetic layer and a Zn component in a nonmagnetic sheet to form an interdiffusion layer in a region of the nonmagnetic sheet inside a conductive pattern. This method allows the interdiffusion layer to be formed without need for complicated processing of the nonmagnetic sheet. Furthermore, there is no boundary region between the magnetic layer and the nonmagnetic sheet around it. The nonmagnetic layer is located between turns of a coiled conductor to suppress degradation of dc bias characteristics and a magnetic body penetrates in a region inside the coiled conductor to suppress reduction in inductance due to provision of the nonmagnetic layer between turns of the coiled conductor.
摘要翻译：一种制造方法，其包括磁性层中的Ni成分的相互扩散和非磁性片中的Zn成分，以在导电图案内部的非磁性片的区域中形成相互扩散层。该方法允许形成相互扩散层，而不需要非磁性片的复杂处理。此外，在磁性层和其周围的非磁性片之间没有边界区域。非磁性层位于线圈导体的匝之间，以抑制直流偏置特性的劣化，并且磁体穿过线圈导体内部的区域，以抑制由于在线圈导体的匝之间提供非磁性层而导致的电感降低。

2. 发明授权

US07691649B2 Method for evaluating impurity distribution under gate electrode without damaging silicon substrate 失效
标题翻译：评估栅极电极杂质分布而不损坏硅衬底的方法
公开(公告)号：US07691649B2
公开(公告)日：2010-04-06
申请号：US11407918
申请日：2006-04-21
申请人： Kazuo Hashimi , Hidekazu Sato
发明人： Kazuo Hashimi , Hidekazu Sato
IPC分类号： H01L21/66 , H01L29/94
CPC分类号： H01L29/66545 , H01L21/32135 , H01L22/12 , H01L29/66681 , H01L29/7836 , H01L2924/0002 , H01L2924/00
摘要： A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. According to the evaluation method, a gate electrode made of a silicon containing material is removed without removing a gate insulating film by contacting pyrolysis hydrogen generated by pyrolysis to the semiconductor device that includes the gate electrode arranged on a semiconductor substrate through a gate insulating film, and a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. Further, a processed form of the gate is evaluated by observing a form of the gate insulating film that remains on the semiconductor substrate, the gate insulating film that remains on the semiconductor substrate is removed by a wet process, and the impurities distribution under the gate is measured and evaluated.
摘要翻译：公开了一种稳定且正确地评估半导体器件的栅极下的杂质分布而不损坏硅衬底的方法。根据评价方法，通过将由热解产生的热解氢接触到包括通过栅极绝缘膜设置在半导体衬底上的栅极的半导体器件的半导体器件，除去栅极绝缘膜而除去含硅材料的栅电极，以及形成在栅电极的相应侧上的半导体衬底上的源电极和漏电极。此外，通过观察保留在半导体衬底上的栅极绝缘膜的形式来评估栅极的处理形式，通过湿法除去保留在半导体衬底上的栅极绝缘膜，并且栅极下的杂质分布被测量和评估。

3. 发明申请

US20080035955A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080035955A1
公开(公告)日：2008-02-14
申请号：US11878509
申请日：2007-07-25
申请人： Hidekazu Sato , Toshihiro Wakabayashi
发明人： Hidekazu Sato , Toshihiro Wakabayashi
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： By a non-selective epitaxial growth method, an SiGe film is grown on the whole surface of a silicon oxide film so as to cover an inner wall of a base opening. Here, such film forming conditions are selected that, inside the base opening, a bottom portion is formed of single crystal, other portions such as a sidewall portion are formed of polycrystalline, and a film thickness of the sidewall portion is less than or equal to 1.5 times the film thickness of the bottom portion. In this non-selective epitaxial growth, monosilane, hydrogen, diborane, and germane are used as source gases. Then, flow rates of monosilane and hydrogen are set to 20 sccm and 20 slm respectively. Also, a growth temperature is set to 650° C., a flow rate of diborane is set to 75 sccm, and a flow rate of germane is set to 35 sccm.
摘要翻译：通过非选择性外延生长方法，在氧化硅膜的整个表面上生长SiGe膜，以覆盖基部开口的内壁。这里，选择这样的成膜条件，即，在基底开口内部，由单晶形成底部，其它部分如侧壁部分由多晶形成，侧壁部分的膜厚小于或等于底部的膜厚度的1.5倍。在这种非选择性外延生长中，使用甲硅烷，氢，乙硼烷和锗烷作为源气体。然后，甲硅烷和氢气的流量分别设定为20sccm和20slm。此外，将生长温度设定为650℃，将乙硼烷的流量设定为75sccm，将锗烷的流量设定为35sccm。

4. 发明申请

US20070138561A1 Semiconductor device, a manufacturing method thereof, and an evaluation method of the semiconductor device 失效
标题翻译：半导体装置及其制造方法以及半导体装置的评价方法
公开(公告)号：US20070138561A1
公开(公告)日：2007-06-21
申请号：US11407918
申请日：2006-04-21
申请人： Kazuo Hashimi , Hidekazu Sato
发明人： Kazuo Hashimi , Hidekazu Sato
IPC分类号： H01L29/94
CPC分类号： H01L29/66545 , H01L21/32135 , H01L22/12 , H01L29/66681 , H01L29/7836 , H01L2924/0002 , H01L2924/00
摘要： A method of stably and correctly evaluating impurities distribution under a gate of a semiconductor device without damaging a silicon substrate is disclosed. According to the evaluation method, a gate electrode made of a silicon containing material is removed without removing a gate insulating film by contacting pyrolysis hydrogen generated by pyrolysis to the semiconductor device that includes the gate electrode arranged on a semiconductor substrate through a gate insulating film, and a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. Further, a processed form of the gate is evaluated by observing a form of the gate insulating film that remains on the semiconductor substrate, the gate insulating film that remains on the semiconductor substrate is removed by a wet process, and the impurities distribution under the gate is measured and evaluated.
摘要翻译：公开了一种稳定且正确地评估半导体器件的栅极下的杂质分布而不损坏硅衬底的方法。根据评价方法，通过将通过热解产生的热解氢接触通过栅极绝缘膜将包含布置在半导体衬底上的栅电极的半导体器件接触而除去栅极绝缘膜而除去含硅材料的栅电极，以及形成在栅电极的相应侧上的半导体衬底上的源电极和漏电极。此外，通过观察保留在半导体衬底上的栅极绝缘膜的形式来评估栅极的处理形式，通过湿法除去保留在半导体衬底上的栅极绝缘膜，并且栅极下的杂质分布被测量和评估。

5. 发明授权

US06903439B2 Bipolar transistor 有权
标题翻译：双极晶体管
公开(公告)号：US06903439B2
公开(公告)日：2005-06-07
申请号：US10665210
申请日：2003-09-22
申请人： Hidekazu Sato , Toshihiro Wakabayashi
发明人： Hidekazu Sato , Toshihiro Wakabayashi
IPC分类号： H01L21/331 , H01L21/8222 , H01L27/082 , H01L27/102 , H01L29/70 , H01L29/73 , H01L29/732 , H01L29/737 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L31/11
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： By a non-selective epitaxial growth method, an SiGe film is grown on the whole surface of a silicon oxide film so as to cover an inner wall of a base opening. Here, such film forming conditions are selected that, inside the base opening, a bottom portion is formed of single crystal, other portions such as a sidewall portion are formed of polycrystalline, and a film thickness of the sidewall portion is less than or equal to 1.5 times the film thickness of the bottom portion. In this nonselective epitaxial growth, monosilane, hydrogen, diborane, and germane are used as source gases. Then, flow rates of monosilane and hydrogen are set to 20 sccm and 20 slm respectively. Also, a growth temperature is set to 650° C., a flow rate of diborane is set to 75 sccm, and a flow rate of germane is set to 35 sccm.
摘要翻译：通过非选择性外延生长方法，在氧化硅膜的整个表面上生长SiGe膜，以覆盖基部开口的内壁。这里，选择这样的成膜条件，即，在基底开口内部，由单晶形成底部，其它部分如侧壁部分由多晶形成，侧壁部分的膜厚小于或等于底部的膜厚度的1.5倍。在这种非选择性外延生长中，使用甲硅烷，氢，乙硼烷和锗烷作为源气体。然后，甲硅烷和氢气的流量分别设定为20sccm和20slm。此外，将生长温度设定为650℃，将乙硼烷的流量设定为75sccm，将锗烷的流量设定为35sccm。

6. 发明申请

US20120181671A1 METHOD FOR EVALUATING IMPURITY DISTRIBUTION UNDER GATE ELECTRODE WITHOUT DAMAGING SILICON SUBSTRATE 失效
标题翻译：在不损坏硅基板的情况下评估栅极电极下的污染物分布的方法
公开(公告)号：US20120181671A1
公开(公告)日：2012-07-19
申请号：US13429804
申请日：2012-03-26
申请人： Kazuo Hashimi , Hidekazu Sato
发明人： Kazuo Hashimi , Hidekazu Sato
IPC分类号： H01L23/544
CPC分类号： H01L29/66545 , H01L21/32135 , H01L22/12 , H01L29/66681 , H01L29/7836 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device forms the semiconductor device in a device region of a semiconductor substrate simultaneously with forming a monitor semiconductor device that includes a gate electrode made of silicon containing material arranged on a gate insulating film in a monitor region of the semiconductor substrate, a source electrode and a drain electrode formed on the semiconductor substrate on corresponding sides of the gate electrode. The gate electrode is removed without removing a gate insulating film by applying pyrolysis hydrogen generated by pyrolysis on the monitor semiconductor device in the monitor region, and the gate insulating film is removed by a wet process. Impurities distribution of a silicon active region appearing after the gate electrode is removed is measured and fed back to a semiconductor manufacturing process.
摘要翻译：半导体器件的制造方法同时形成半导体衬底的器件区域中的半导体器件，同时形成监测半导体器件，该监控半导体器件包括在半导体衬底的监视器区域中布置在栅极绝缘膜上的由含硅材料制成的栅电极，形成在栅电极的相应侧上的半导体衬底上的源电极和漏电极。通过在监视器区域中的监视器半导体器件上施加由热解产生的热解氢，除去栅极绝缘膜，去除栅电极，并通过湿法去除栅极绝缘膜。测量在去除栅电极之后出现的硅有源区的杂质分布并将其反馈到半导体制造工艺。

7. 发明申请

US20090230469A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090230469A1
公开(公告)日：2009-09-17
申请号：US12401007
申请日：2009-03-10
申请人： Hidekazu Sato
发明人： Hidekazu Sato
IPC分类号： H01L29/06 , H01L21/71
CPC分类号： H01L29/42364 , H01L21/823412 , H01L21/823462 , H01L27/088 , H01L29/0638 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/456 , H01L29/66681 , H01L29/7816
摘要： A method of manufacturing a semiconductor device is provided which comprises: forming a first gate insulating film and a second gate insulating film in an active region of a semiconductor substrate; introducing an impurity of a first conductivity type into a first site where a first body region is to be formed, the first site being disposed under the first gate insulating film in the active region; forming a gate electrode on each of the first gate insulating film and the second gate insulating film; and introducing an impurity of the first conductivity type into the first site and a second site where a second body region is to be formed, the second site being disposed under the second gate insulating film in the active region, to form the first body region and the second body region, respectively.
摘要翻译：提供一种制造半导体器件的方法，其包括：在半导体衬底的有源区中形成第一栅极绝缘膜和第二栅极绝缘膜; 将第一导电类型的杂质引入要形成第一体区的第一位置，所述第一位置设置在所述有源区中的所述第一栅极绝缘膜下方; 在所述第一栅极绝缘膜和所述第二栅极绝缘膜的每一个上形成栅电极; 并且将第一导电类型的杂质引入到第一部位和形成第二体区的第二部位，第二部位设置在有源区的第二栅极绝缘膜的下方，形成第一体区，第二体区。

8. 发明申请

US20070181910A1 Heterobipolar transistor and method of fabricating the same 有权
标题翻译：异相晶体管及其制造方法
公开(公告)号：US20070181910A1
公开(公告)日：2007-08-09
申请号：US11445240
申请日：2006-06-02
申请人： Hidekazu Sato , Takae Sukegawa , Kousuke Suzuki
发明人： Hidekazu Sato , Takae Sukegawa , Kousuke Suzuki
IPC分类号： H01L31/00
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/1608 , H01L29/7378
摘要： The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher than the concentration of carbon on the side bordering on the emitter layer, and upon the formation of the emitter layer, both boron and carbon are dispersed into a portion of the emitter layer that comes into contact with the base layer.
摘要翻译：本发明实现了使用SiGeC基层的异双极晶体管，以改善其电特性。具体地说，控制基底层内的碳和硼的分布，使得硼的浓度高于与发射极层相邻的一侧的碳浓度，并且在形成发射极层时，硼和碳都是分散到与基底层接触的发射极层的一部分。

9. 发明授权

US07194507B2 Method and apparatus for setting communication parameter in information terminal 有权
标题翻译：在信息终端中设置通信参数的方法和装置
公开(公告)号：US07194507B2
公开(公告)日：2007-03-20
申请号：US10069831
申请日：2001-06-27
申请人： Hidekazu Sato , Hidekazu Fukai
发明人： Hidekazu Sato , Hidekazu Fukai
IPC分类号： G06F15/16
CPC分类号： G06Q10/02 , H04L12/2856 , H04L41/0806 , H04L41/0843 , H04L41/0886 , H04L67/34 , H04L69/24
摘要： A communication parameter delivery server 50b has communication parameters necessary for making each of information terminals 13, 23 and 33 have a dial-up IP connection service. The server 50b delivers the communication parameters via each of networks 12, 22 and 33 responsively to a request from each of the information terminals 13, 23 and 33. The delivered communication terminals are set to Internet connection software installed in each of the information terminal 13, 23 and 33.
摘要翻译：通信参数传递服务器50b具有使信息终端13,23和33中的每一个具有拨号IP连接服务所必需的通信参数。响应于来自每个信息终端13,23和33的请求，服务器50b经由网络12,22和33中的每一个递送通信参数。传送的通信终端被设置为安装在信息终端13,23和33的每一个中的因特网连接软件。

10. 发明申请

US20060006477A1 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060006477A1
公开(公告)日：2006-01-12
申请号：US11114111
申请日：2005-04-26
申请人： Kazuo Hashimi , Hidekazu Sato
发明人： Kazuo Hashimi , Hidekazu Sato
IPC分类号： H01L29/76 , H01L21/302 , H01L21/26
CPC分类号： H01L29/66636 , H01L21/02063 , H01L21/02071 , H01L21/3065 , H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process.
摘要翻译：半导体器件制造方法包括以下步骤：（a）在半导体衬底上形成电介质膜; （b）通过干法蚀刻电介质膜; 和（c）在规定的温度条件下，在半导体衬底上提供热分解的原子氢，以除去由于干法而在半导体衬底中产生的损伤层。

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