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    • 9. 发明授权
    • Vector data processing apparatus wherein a time slot for access to a
bank of vector registors is assigned based on memory access time
information
    • 矢量数据处理装置,其中基于存储器访问时间信息分配用于访问一组向量注册器的时隙
    • US5539902A
    • 1996-07-23
    • US460390
    • 1995-06-02
    • Kenichi SakaiKazushi SakamotoShoji Nakatani
    • Kenichi SakaiKazushi SakamotoShoji Nakatani
    • G06F9/38G06F15/78G06F13/372
    • G06F9/3887G06F15/8084G06F9/30036G06F9/3877
    • A vector data processing apparatus having a set of vector registers, one or more memory access pipelines, and one or more composite calculation pipelines, wherein the vector registers consist of a plurality of banks, and each bank is independently accessible. Each of the pipelines can cyclically access each of the banks of the vector registers when one or more of a predetermined number of time slots, through each of which time slots the access is carried out, are assigned to an instruction using the pipeline. Immediately when a memory access instruction is received, a vector unit control circuit, which controls operations of the vector data processing apparatus, assigns a time slot for a newly-detected memory access instruction using a memory access pipeline, if it is determined that the memory access pipeline is available based on the pipeline operation status flags, and that the time slot is available based on the detected status of the predetermined number of time slots. Further, when a composite calculation instruction is received, the vector unit control circuit assigns one or more time slots .for the newly-detected composite calculation instruction using a composite calculation pipeline, if it is determined that the composite calculation pipeline is available based on the pipeline operation status flags, and that time slots are available based on the detected status of the predetermined number of time slots.
    • 一种矢量数据处理装置,具有一组向量寄存器,一个或多个存储器访问管线以及一个或多个复合计算流水线,其中矢量寄存器由多个存储体组成,每个存储体可独立存取。 当通过每个时隙执行访问的预定数量的时隙中的一个或多个被分配给使用流水线的指令时,每个流水线可以周期性地访问矢量寄存器的每个组。 当接收到存储器访问指令时,如果确定存储器访问指令,那么控制向量数据处理设备的操作的向量单元控制电路立即使用存储器访问管道为新检测的存储器访问指令分配时隙 基于流水线操作状态标志可获得访问流水线,并且基于检测到的预定数量的时隙的状态,该时隙可用。 此外,当接收到复合计算指令时,矢量单元控制电路使用复合计算流水线为新检测的复合计算指令分配一个或多个时隙,如果基于该复合计算指令可以确定复合计算管道可用 流水线运行状态标志,并且根据检测到的预定数量的时隙的状态可用该时隙。
    • 10. 发明授权
    • Vector access control system
    • 矢量门禁系统
    • US4870569A
    • 1989-09-26
    • US929818
    • 1986-11-13
    • Shoji NakataniKazushi Sakamoto
    • Shoji NakataniKazushi Sakamoto
    • G06F17/16G06F12/02G06F15/78
    • G06F15/8061G06F12/0207
    • A vector access control system for a computer system is provided, including vector registers and a memory access pipeline function unit having an indirect address match checking circuit for detecting a coincidence between data of elements accessed by a plurality of indirect address data. An access to a main storage is carried out by adding a plurality of data, which are read from the vector registers and are necessary for an indirect address access, to a leading address. When a coincidence of data of elements and a resultant conflict between access requests to the main storage is detected by the indirect address match checking circuit, only a predetermined access request in the conflicting access requests is allowed.
    • 提供了一种用于计算机系统的向量访问控制系统,包括向量寄存器和具有间接地址匹配检查电路的存储器访问管道功能单元,用于检测由多个间接地址数据访问的元素的数据之间的一致性。 通过将从向量寄存器读取并且对于间接地址访问所必需的多个数据添加到前导地址来执行对主存储器的访问。 当通过间接地址匹配检查电路检测到元件的数据的一致性和对主存储器的访问请求之间的结果冲突时,只允许冲突访问请求中的预定访问请求。