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1. 发明授权

US06634023B1 Compile method, exception handling method and computer 有权
公开(公告)号：US06634023B1
公开(公告)日：2003-10-14
申请号：US09334789
申请日：1999-06-16
申请人： Hideaki Komatsu , Takeshi Oqasawara
发明人： Hideaki Komatsu , Takeshi Oqasawara
IPC分类号： G06F945
CPC分类号： G06F8/445
摘要： The present invention enables re-ordering of instructions to be executed while assuring a precise exception. In Java language, an optimization process of re-ordering instructions to be executed is performed by Just-In-Time compiler. For instance, the instructions lining in order from instruction E1 which was moved forward to instruction S2which had been located before E1 is registered as interrupt inhibited section R1, and from instruction S4 which was moved forward to instruction S3 which had been located before S4 is registered as interrupt inhibited section R2 (S is an instruction which has an affect observable from the outside at the execution, and E is an instruction which may cause an exception). Also, in FIG. 7, S4 which was an instruction behind E1 in the original order is registered as R1's instruction invalid at an exception. If E1 causes an exception, an interrupt handler is activated and the instructions of interrupt inhibited section R1 are copied to another area. S4 is not copied in that case. In addition, a branch code to an exception handling routine is attached to the end of the copy. If execution is restarted from S1, the instructions required to be executed for assuring the precise exception are executed, and it may move on to an exception handling routine thereafter.

2. 发明授权

US09298419B2 Merging sorted data arrays based on vector minimum, maximum, and permute instructions 有权
标题翻译：根据向量最小值，最大值和置换指令合并排序的数据数组
公开(公告)号：US09298419B2
公开(公告)日：2016-03-29
申请号：US13601177
申请日：2012-08-31
申请人： Hiroshi Inoue , Moriyoshi Ohara , Hideaki Komatsu
发明人： Hiroshi Inoue , Moriyoshi Ohara , Hideaki Komatsu
IPC分类号： G06F7/36 , G06F9/30 , G06F9/38
CPC分类号： G06F7/36 , G06F9/3001 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/3885 , G06F9/3887
摘要： A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with mitigated or removed conditional branching. The merge operations of the streams of data include Merge AND and Merge OR operations.
摘要翻译：提供了一种通过使用SIMD指令来执行两个或更多个数据流的有效合并操作的方法和装置。数据流并行并入缓冲或移除条件分支。数据流的合并操作包括合并和和合并或运算。

3. 发明授权

US09251308B2 Simulation method, system, and program 有权
标题翻译：仿真方法，系统和程序
公开(公告)号：US09251308B2
公开(公告)日：2016-02-02
申请号：US13555731
申请日：2012-07-23
申请人： Kohichi Kajitani , Hideaki Komatsu , Shu Shimizu
发明人： Kohichi Kajitani , Hideaki Komatsu , Shu Shimizu
IPC分类号： G06F17/50 , B60T8/40 , G06F11/36
CPC分类号： G06F17/5095 , B60T8/4081 , G06F11/3632 , G06F17/5009 , G06F2217/86
摘要： System and method for achieving reproducibility of a simulation operation while reasonably keeping an operation speed. A peripheral scheduler clears completion flags of all the peripheral emulators to thereby start parallel operations thereof. Then, based on processing break timing set for the individual peripheral emulators, the peripheral scheduler finds one of the peripheral emulators which is scheduled to reach a processing break at the earliest. The found peripheral emulator is referred to as a peripheral P. In a case where a time of the processing break of the peripheral P is T, the peripheral scheduler continues execution of processor emulators and plant simulators up until a time point of the time T. The peripheral scheduler waits for setting of a completion flag of the peripheral P. In response to the setting, the peripheral scheduler performs data synchronization among the peripheral P, the processor emulators, and the plant simulators.
摘要翻译：在合理保持操作速度的同时实现模拟操作的再现性的系统和方法。外设调度器清除所有外围仿真器的完成标志，从而开始其并行操作。然后，基于针对各个外围仿真器设置的处理中断定时，外围调度器发现最早计划到达处理中断的外围仿真器之一。所寻找的外设仿真器被称为外设P.在外设P的处理中断的时间为T的情况下，外围调度器继续执行处理器仿真器和工厂模拟器直到时间T的时间点。外设调度器等待设置外设P的完成标志。响应于该设置，外围调度器在外设P，处理器模拟器和工厂模拟器之间执行数据同步。

4. 发明授权

US08959498B2 Parallelization method, system and program 有权
标题翻译：并行化方法，系统和程序
公开(公告)号：US08959498B2
公开(公告)日：2015-02-17
申请号：US13031666
申请日：2011-02-22
申请人： Hideaki Komatsu , Takeo Yoshizawa
发明人： Hideaki Komatsu , Takeo Yoshizawa
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A parallelization method, system and program. A program expressed by a block diagram or the like is divided into strands and a balance in calculation time is made among the strands. The functional blocks are divided into strands and the strand involving the maximum calculation time from a strand set is found. One or more movable blocks in the strand involving the maximum calculation time is found. The next step is obtaining calculation time of each strand after the movable block is moved to the strand in the input or output direction according to its property, and moving the block to a strand most largely reducing the calculation time of the strand having the maximum calculation time before the movement. This process loops until calculation time is no longer reduced. Strands are then transformed into source codes. Source codes are compiled and assigned to separate cores or processors for execution.
摘要翻译：并行化方法，系统和程序。通过框图等表示的程序被划分成多个线，并且在线之间进行计算时间的平衡。功能块被划分为股线，并且发现涉及从股线组得到的最大计算时间的股线。发现涉及最大计算时间的股份中的一个或多个可移动块。下一步是根据其可移动块在输入或输出方向上移动到股线之后获得每条股的计算时间，并且将块移动到股线，最大程度上减少具有最大计算的股线的计算时间运动前的时间。此过程循环，直到计算时间不再减少。然后将链条转换为源代码。源代码被编译并分配给单独的核心或处理器以供执行。

5. 发明授权

US08868381B2 Control system design simulation using switched linearization 有权
标题翻译：使用开关线性化的控制系统设计仿真
公开(公告)号：US08868381B2
公开(公告)日：2014-10-21
申请号：US12961479
申请日：2010-12-06
申请人： Hideaki Komatsu , Hitomi Takahashi , Gang Zhang
发明人： Hideaki Komatsu , Hitomi Takahashi , Gang Zhang
IPC分类号： G06F17/50 , G06F11/36 , G05B19/406 , G05B19/4061 , G05B19/4063 , G06F1/03 , G05B17/00 , G05B23/02 , G06F17/10 , G06F9/44 , G05B13/04
CPC分类号： G06F17/5009 , G05B13/04 , G05B17/00 , G05B19/406 , G05B19/4061 , G05B19/4063 , G05B23/0205 , G05B23/0243 , G06F1/03 , G06F8/34 , G06F11/3668 , G06F17/10
摘要： A method converts a plurality of functional blocks into linear blocks such that the nonlinear blocks are divided into a plurality of states through switched linearization. The plurality of states generated by said switched linearization is then transitioned selectively based on a predetermined operational scenario. Each state is then tested separately to ensure that implementation of the states are safe. A first guard block is provided when a state is deemed unsafe such that the first guard block is enabled to cause a system shutdown so as to prevent further processing that can cause an unsafe result.
摘要翻译：一种方法将多个功能块转换成线性块，使得非线性块通过切换线性化被分成多个状态。然后，基于预定的操作场景选择性地转换由所述切换线性化产生的多个状态。然后单独测试每个状态，以确保状态的实现是安全的。当状态被视为不安全时，提供第一保护块，使得第一保护块能够使系统关闭，以防止可能导致不安全结果的进一步处理。

6. 发明授权

US08677334B2 Parallelization method, system and program 失效
标题翻译：并行化方法，系统和程序
公开(公告)号：US08677334B2
公开(公告)日：2014-03-18
申请号：US12913822
申请日：2010-10-28
申请人： Arquimedes Martinez Canedo , Hideaki Komatsu , Takeo Yoshizawa
发明人： Arquimedes Martinez Canedo , Hideaki Komatsu , Takeo Yoshizawa
IPC分类号： G06F9/45
CPC分类号： G06F11/261
摘要： A computer-implemented method, system, and article of manufacture for parallelizing a code configured by coupling a functional block having an internal state and a functional block without any internal state. The method includes: creating and storing a graphical representation where functional blocks are chosen as nodes and connections between functional blocks are chosen as links; visiting the nodes on the graphical representation sequentially, detecting inputs from functional blocks without any internal state to functional blocks having an internal state and storing these functional blocks as a set of use blocks, and detecting inputs from functional blocks having an internal state to functional blocks without any internal state and storing these functional blocks as a set of definition blocks; and forming strands of functional blocks based on information on the set of use blocks and information on the set of definition blocks stored in association with the functional blocks.
摘要翻译：一种用于并行化代码的计算机实现的方法，系统和制品，其通过耦合具有内部状态的功能块和功能块而没有任何内部状态来配置。该方法包括：创建和存储其中功能块被选择为节点的图形表示，并且功能块之间的连接被选择为链接; 在图形表示上顺序地访问节点，检测来自功能块的输入，而没有任何内部状态到具有内部状态的功能块，并将这些功能块存储为一组使用块，并且检测具有内部状态的功能块到功能块的输入没有任何内部状态并将这些功能块存储为一组定义块; 以及基于关于所述使用块集合的信息和与所述功能块相关联地存储的所述定义块集合上的信息来形成功能块组。

7. 发明授权

US08676560B2 Simulation method, system and program for simulating physical unit controlled by electronic control unit 失效
标题翻译：用于模拟由电子控制单元控制的物理单元的仿真方法，系统和程序
公开(公告)号：US08676560B2
公开(公告)日：2014-03-18
申请号：US12481105
申请日：2009-06-09
申请人： Koichi Kajitani , Hideaki Komatsu , Shuichi Shimizu
发明人： Koichi Kajitani , Hideaki Komatsu , Shuichi Shimizu
IPC分类号： G06F17/50 , G06F9/455 , G06G7/62
CPC分类号： G06F17/5022 , G06F2217/86
摘要： In a normal operation, a physical unit simulator is allowed to speculatively perform high-speed continuous execution. Only when an actual input comes in, a speculative input and the actual input are compared with each other. Thereafter, in response to inconsistency between the inputs, the physical unit simulator is returned to a point closest to the point of the actual input and is allowed to execute a variable step module to reach the point of the actual input. Upon arrival at the point of the actual input, the simulator is shifted back to the high-speed continuous execution from there. Thus, a processing speed of the simulator can be significantly improved.
摘要翻译：在正常操作中，允许物理单元模拟器推测地执行高速连续执行。只有当实际输入进入时，推测输入和实际输入才能相互比较。此后，响应于输入之间的不一致，物理单元模拟器返回到最接近实际输入点的点，并允许执行可变步长模块以达到实际输入点。在到达实际输入点时，模拟器从那里转回高速连续执行。因此，可以显着地提高模拟器的处理速度。

8. 发明授权

US08670967B2 Simulation method, system and article of manufacture 有权
标题翻译：仿真方法，系统和制造
公开(公告)号：US08670967B2
公开(公告)日：2014-03-11
申请号：US13255938
申请日：2010-03-10
申请人： Hideaki Komatsu , Fimitomo Ohsawa , Shuichi Shimizu
发明人： Hideaki Komatsu , Fimitomo Ohsawa , Shuichi Shimizu
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G05B17/02 , G06F17/5095 , Y02T10/82
摘要： A simulation system, method, and article of manufacture. A simulation system has a discrete and a continuous portion. The discrete portion further has a peripheral emulator in communication with the continuous portion of the simulation system. A portion of a peripheral emulator is separated and is caused to operate in a thread of a continuous system. The continuous system and the peripheral are in loose synchronization and therefore sparsely communicate with each other. The configuration significantly reduces the frequency of inter-thread communications between the continuous system and the discrete system that are performed in response to a continuous clock in a simulation system including the continuous system and the discrete system, thereby reducing communication cost. Accordingly, the operation speed of the simulation system can be increased.
摘要翻译：模拟系统，方法和制造。模拟系统具有离散和连续的部分。离散部分还具有与仿真系统的连续部分通信的外围仿真器。外围仿真器的一部分被分离并且使其在连续系统的线程中操作。连续系统和外围设备处于松动同步状态，因此彼此稀疏地通信。该配置显着地降低了在包括连续系统和离散系统的模拟系统中响应于连续时钟而执行的连续系统和离散系统之间的线程间通信的频率，从而降低通信成本。因此，能够提高模拟系统的运转速度。

9. 发明授权

US08555270B2 Profile-based global live-range splitting 失效
标题翻译：基于配置文件的全球实况分割
公开(公告)号：US08555270B2
公开(公告)日：2013-10-08
申请号：US11380833
申请日：2006-04-28
申请人： Takuya Nakaike , Tatsushi Inagaki , Hideaki Komatsu
发明人： Takuya Nakaike , Tatsushi Inagaki , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/433 , G06F8/441 , G06F8/443
摘要： A method and system are provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph.
摘要翻译：提供了一种方法和系统，用于在频繁执行的程序指令区域中分割变量的实时范围。变量的实时范围被分成多个子范围，每个子范围可以分配给不同的寄存器或溢出到存储器中。在频繁使用的代码区域中，通过在控制流程图中的每个连接点和分支点分割活动范围之后获得的简档信息来聚合生存范围，减少了经常使用的代码区域的数量。

10. 发明申请

US20130103829A1 COMPUTER SYSTEM, METHOD, AND PROGRAM 有权
标题翻译：计算机系统，方法和程序
公开(公告)号：US20130103829A1
公开(公告)日：2013-04-25
申请号：US13695558
申请日：2011-04-21
申请人： Munehiro Doi , Hideaki Komatsu , Kumiko Maeda , Masana Murase , Takeo Yoshizawa
发明人： Munehiro Doi , Hideaki Komatsu , Kumiko Maeda , Masana Murase , Takeo Yoshizawa
IPC分类号： H04L12/26
CPC分类号： H04L43/04 , G06F9/485
摘要： Traffic data while the system is in operation is collected for a certain time as a preprocess. Typical patterns are extracted from the collected traffic data. Next, stream programs are created for the individual typical patterns and stored for the future reference. Next, the IDs of alternative tasks for transition among different stream programs are stored. In actual system operation, the system measures traffic data regularly or at any time, compares the resultant patterns with the typical patterns, and selects a stream program corresponding to the closest typical pattern as the next phase. Program shutdown time when shifting from the stream program in the present phase to the next phase can be reduced by gradually shifting empty tasks in the present phase to the next stream program as alternative tasks in consideration of the cost of switching between tasks, the cost of transferring data among resources, and so on.
摘要翻译：系统运行时的流量数据作为预处理收集一段时间。从收集的交通数据中提取典型模式。接下来，为各个典型模式创建流程序，并存储以供将来参考。接下来，存储用于不同流程序之间的转换的替代任务的ID。在实际系统运行中，系统定期或随时测量交通数据，将结果模式与典型模式进行比较，并选择与最接近的典型模式对应的流程序作为下一阶段。考虑到任务之间的切换成本，可以通过逐渐将当前阶段的空任务逐步转移到下一个流程序来将程序关闭时间从当前阶段的流程序转换到下一阶段，成本资源之间传输数据等等。

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