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1. 发明授权

US08219760B2 Storage subsystem and its control method 有权
标题翻译：存储子系统及其控制方法
公开(公告)号：US08219760B2
公开(公告)日：2012-07-10
申请号：US12526663
申请日：2009-04-06
申请人： Hideaki Fukuda , Nobuyuki Minowa , Naoki Moritoki , Masanori Takada , Masato Shimizu
发明人： Hideaki Fukuda , Nobuyuki Minowa , Naoki Moritoki , Masanori Takada , Masato Shimizu
IPC分类号： G06F13/00 , G06F12/14
CPC分类号： G06F3/0659 , G06F3/0614 , G06F3/0637 , G06F3/0658 , G06F3/0683 , G06F12/0284 , G06F12/1458 , G06F12/1483
摘要： Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.
摘要翻译：提供了一种存储子系统，即使从处理器核心到开关电路的未经授权的访问，通过将多核系统应用于处理器，也能够维持对主机设备的I / O处理的可靠性。多核处理器被应用于不同于第一逻辑地址空间的第二逻辑地址空间，以将其通常应用于多个受控单元，例如由处理器访问的主机接口。开关电路基于属于第二地址空间的地址确定发出访问的处理器核心，并将包含在从处理器核心的访问中的地址映射到第一地址空间的地址。

2. 发明申请

US20110296117A1 STORAGE SUBSYSTEM AND ITS CONTROL METHOD 有权
标题翻译：存储子系统及其控制方法
公开(公告)号：US20110296117A1
公开(公告)日：2011-12-01
申请号：US12526663
申请日：2009-04-06
申请人： Hideaki Fukuda , Nobuyuki Minowa , Naoki Moritoki , Masanori Takada , Masato Shimizu
发明人： Hideaki Fukuda , Nobuyuki Minowa , Naoki Moritoki , Masanori Takada , Masato Shimizu
IPC分类号： G06F13/00
CPC分类号： G06F3/0659 , G06F3/0614 , G06F3/0637 , G06F3/0658 , G06F3/0683 , G06F12/0284 , G06F12/1458 , G06F12/1483
摘要： Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.
摘要翻译：提供了一种存储子系统，即使从处理器核心到开关电路的未经授权的访问，通过将多核系统应用于处理器，也能够维持对主机设备的I / O处理的可靠性。多核处理器被应用于不同于第一逻辑地址空间的第二逻辑地址空间，以将其通常应用于多个受控单元，例如由处理器访问的主机接口。开关电路基于属于第二地址空间的地址确定发出访问的处理器核心，并将包含在从处理器核心的访问中的地址映射到第一地址空间的地址。

3. 发明授权

US07697311B2 Storage apparatus, controller and control method 失效
标题翻译：储存装置，控制器及控制方法
公开(公告)号：US07697311B2
公开(公告)日：2010-04-13
申请号：US12259468
申请日：2008-10-28
申请人： Hideaki Fukuda , Naoki Moritoki
发明人： Hideaki Fukuda , Naoki Moritoki
IPC分类号： G11C15/00
CPC分类号： G06F12/0868 , G06F3/061 , G06F3/0616 , G06F3/0646 , G06F3/0655 , G06F3/0656 , G06F3/068 , G06F2212/217 , Y02D10/13
摘要： Proposed is a highly reliable storage apparatus with fast access speed and low power consumption, as well as a controller and control method for controlling such a storage apparatus. This storage apparatus is equipped with a flash memory that provides a storage extent for storing data, a disk-shaped memory device with more data write cycles than the flash memory, and a cache memory with faster access speed than the flash memory. Data provided from a host system is stored in the cache memory, this data is read from the cache memory at a prescribed timing, data read from the cache memory is stored in the disk-shaped memory device, and, when a prescribed condition is satisfied, this data is read from the disk-shaped memory device, and the data read from the disk-shaped memory device is stored in the flash memory.
摘要翻译：提出了具有快速访问速度和低功耗的高度可靠的存储装置，以及用于控制这种存储装置的控制器和控制方法。该存储装置配备有提供用于存储数据的存储范围的闪速存储器，具有比闪存更多的数据写入周期的盘形存储器件，以及具有比闪存更快的存取速度的高速缓存存储器。从主机系统提供的数据被存储在高速缓冲存储器中，在规定的时刻从高速缓冲存储器读出该数据，从高速缓冲存储器读出的数据存储在盘状存储装置中，并且当满足规定的条件时从盘状存储装置读取该数据，从盘状存储装置读取的数据存储在闪速存储器中。

4. 发明申请

US20080086585A1 STORAGE APPARATUS, CONTROLLER AND CONTROL METHOD 有权
标题翻译：存储设备，控制器和控制方法
公开(公告)号：US20080086585A1
公开(公告)日：2008-04-10
申请号：US11563855
申请日：2006-11-28
申请人： Hideaki Fukuda , Naoki Moritoki
发明人： Hideaki Fukuda , Naoki Moritoki
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0868 , G06F3/061 , G06F3/0616 , G06F3/0646 , G06F3/0655 , G06F3/0656 , G06F3/068 , G06F2212/217 , Y02D10/13
摘要： Proposed is a highly reliable storage apparatus with fast access speed and low power consumption, as well as a controller and control method for controlling such a storage apparatus. This storage apparatus is equipped with a flash memory that provides a storage extent for storing data, a disk-shaped memory device with more data write cycles than the flash memory, and a cache memory with faster access speed than the flash memory. Data provided from a host system is stored in the cache memory, this data is read from the cache memory at a prescribed timing, data read from the cache memory is stored in the disk-shaped memory device, and, when a prescribed condition is satisfied, this data is read from the disk-shaped memory device, and the data read from the disk-shaped memory device is stored in the flash memory.
摘要翻译：提出了具有快速访问速度和低功耗的高度可靠的存储装置，以及用于控制这种存储装置的控制器和控制方法。该存储装置配备有提供用于存储数据的存储范围的闪速存储器，具有比闪存更多的数据写入周期的盘形存储器件，以及具有比闪存更快的存取速度的高速缓冲存储器。从主机系统提供的数据被存储在高速缓冲存储器中，在规定的时刻从高速缓冲存储器读出该数据，从高速缓冲存储器读出的数据存储在盘状存储装置中，并且当满足规定的条件时从盘状存储装置读取该数据，从盘状存储装置读取的数据存储在闪速存储器中。

5. 发明授权

US07460383B2 Storage apparatus, controller and control method 有权
标题翻译：储存装置，控制器及控制方法
公开(公告)号：US07460383B2
公开(公告)日：2008-12-02
申请号：US11563855
申请日：2006-11-28
申请人： Hideaki Fukuda , Naoki Moritoki
发明人： Hideaki Fukuda , Naoki Moritoki
IPC分类号： G11C15/00
CPC分类号： G06F12/0868 , G06F3/061 , G06F3/0616 , G06F3/0646 , G06F3/0655 , G06F3/0656 , G06F3/068 , G06F2212/217 , Y02D10/13
摘要： Proposed is a highly reliable storage apparatus with fast access speed and low power consumption, as well as a controller and control method for controlling such a storage apparatus. This storage apparatus is equipped with a flash memory that provides a storage extent for storing data, a disk-shaped memory device with more data write cycles than the flash memory, and a cache memory with faster access speed than the flash memory. Data provided from a host system is stored in the cache memory, this data is read from the cache memory at a prescribed timing, data read from the cache memory is stored in the disk-shaped memory device, and, when a prescribed condition is satisfied, this data is read from the disk-shaped memory device, and the data read from the disk-shaped memory device is stored in the flash memory.
摘要翻译：提出了具有快速访问速度和低功耗的高度可靠的存储装置，以及用于控制这种存储装置的控制器和控制方法。该存储装置配备有提供用于存储数据的存储范围的闪速存储器，具有比闪存更多的数据写入周期的盘形存储器件，以及具有比闪存更快的存取速度的高速缓冲存储器。从主机系统提供的数据被存储在高速缓冲存储器中，在规定的时刻从高速缓冲存储器读出该数据，从高速缓冲存储器读出的数据存储在盘状存储装置中，并且当满足规定的条件时从盘状存储装置读取该数据，从盘状存储装置读取的数据存储在闪速存储器中。

6. 发明申请

US20110246720A1 STORAGE SYSTEM WITH MULTIPLE CONTROLLERS 有权
标题翻译：具有多个控制器的存储系统
公开(公告)号：US20110246720A1
公开(公告)日：2011-10-06
申请号：US12668721
申请日：2009-11-10
申请人： Shuji Nakamura , Emi Nakamura , Masahiro Arai , Hideaki Fukuda , Nobuyuki Minowa
发明人： Shuji Nakamura , Emi Nakamura , Masahiro Arai , Hideaki Fukuda , Nobuyuki Minowa
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0813 , G06F12/0868 , G06F2212/284 , G06F2212/286
摘要： A first controller, and a second controller coupled to the first controller via a first path are provided. The first controller includes a first relay circuit which is a circuit that controls data transfer, and a first processor coupled to the first relay circuit via a first second path. The second controller includes a second relay circuit which is a circuit that controls data transfer, and is coupled to the first relay circuit via the first path, and a second processor coupled to the second relay circuit via a second second path. The first processor is coupled to the second relay circuit not via the first relay circuit but via a first third path, and accesses the second relay circuit via the first third path during an I/O process. The second processor is coupled to the first relay circuit not via the second relay circuit but via a second third path, and accesses the first relay circuit via the second third path during an I/O process.
摘要翻译：提供了经由第一路径耦合到第一控制器的第一控制器和第二控制器。第一控制器包括作为控制数据传输的电路的第一继电器电路和经由第一第二路径耦合到第一继电器电路的第一处理器。第二控制器包括第二继电器电路，其是控制数据传输并且经由第一路径耦合到第一继电器电路的电路，以及经由第二第二路径耦合到第二继电器电路的第二处理器。第一处理器不是经由第一继电器电路而是经由第一第三路径耦合到第二继电器电路，并且在I / O过程期间经由第一第三路径访问第二继电器电路。第二处理器不经由第二继电器电路而经由第二第三路径耦合到第一继电器电路，并且在I / O过程期间经由第二第三路径访问第一继电器电路。

7. 发明授权

US08321622B2 Storage system with multiple controllers and multiple processing paths 有权
标题翻译：具有多个控制器和多个处理路径的存储系统
公开(公告)号：US08321622B2
公开(公告)日：2012-11-27
申请号：US12668721
申请日：2009-11-10
申请人： Shuji Nakamura , Emi Nakamura, legal representative , Masahiro Arai , Hideaki Fukuda , Nobuyuki Minowa
发明人： Shuji Nakamura , Masahiro Arai , Hideaki Fukuda , Nobuyuki Minowa
IPC分类号： H04L12/50
CPC分类号： G06F12/0813 , G06F12/0868 , G06F2212/284 , G06F2212/286
摘要： The first controller includes a first relay circuit which is a circuit that controls data transfer, and a first processor coupled to the first relay circuit via a first second path. The second controller includes a second relay circuit which is a circuit that controls data transfer, and is coupled to the first relay circuit via the first path, and a second processor coupled to the second relay circuit via a second second path. The first processor is coupled to the second relay circuit not via the first relay circuit but via a first third path, and accesses the second relay circuit via the first third path during an I/O process. The second processor is coupled to the first relay circuit not via the second relay circuit but via a second third path, and accesses the first relay circuit via the second third path during an I/O process.
摘要翻译：第一控制器包括作为控制数据传输的电路的第一继电器电路和经由第一第二路径耦合到第一继电器电路的第一处理器。第二控制器包括第二继电器电路，其是控制数据传输并且经由第一路径耦合到第一继电器电路的电路，以及经由第二第二路径耦合到第二继电器电路的第二处理器。第一处理器不是经由第一继电器电路而是经由第一第三路径耦合到第二继电器电路，并且在I / O过程期间经由第一第三路径访问第二继电器电路。第二处理器不经由第二继电器电路而经由第二第三路径耦合到第一继电器电路，并且在I / O过程期间经由第二第三路径访问第一继电器电路。

8. 发明申请

US20110296129A1 DATA TRANSFER DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：数据传送装置及其控制方法
公开(公告)号：US20110296129A1
公开(公告)日：2011-12-01
申请号：US12747086
申请日：2010-06-01
申请人： Masahiro Arai , Hiroshi Hirayama , Masanori Takada , Hiroshi Kanayama , Hideaki Fukuda
发明人： Masahiro Arai , Hiroshi Hirayama , Masanori Takada , Hiroshi Kanayama , Hideaki Fukuda
IPC分类号： G06F12/02
CPC分类号： G11C7/10 , G06F13/28 , G06F13/4282 , G06F2213/0026
摘要： A data transfer device that confirms completion of writing into a memory on transferring data to the memory via a bus through which a response indicating completion of data writing in the memory is not sent back includes an inter-memory data transfer control unit performing data transfer between the memories. When the inter-memory data transfer control unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by a procedure different from writing into the memory. When a data transfer with a designated transfer length is completed, in order to confirm that writing is completed as to the write destination memory at the end of the data transfer, the inter-memory data transfer control unit performs confirmation of write completion as to the write destination memory at the end of the transfer by the procedure different from writing into the memory. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of write completion.
摘要翻译：一种数据传送装置，其确认写入到存储器中的写入数据经由经由总线的数据传送到存储器，通过该总线不指示在存储器中写入数据的响应的响应不被发回包括存储器间数据传送控制单元，回忆当存储器间数据传送控制单元检测从第一存储器到第二存储器的写入目的地存储器的切换时，为了确认对第一存储器的写入完成，存储器间数据传送控制单元执行写入的确认通过不同于写入内存的过程来完成第一个内存。当具有指定传送长度的数据传输完成时，为了确认在数据传送结束时关于写入目的地存储器的写入完成，存储器间数据传送控制单元执行关于写入完成的确认通过与写入存储器不同的过程在传送结束时写入目标存储器。存储器间数据传送控制单元基于写入完成的确认通知处理器完成存储器间数据传送。

9. 发明授权

US08572342B2 Data transfer device with confirmation of write completion and method of controlling the same 有权
标题翻译：具有写入完成确认的数据传输设备及其控制方法
公开(公告)号：US08572342B2
公开(公告)日：2013-10-29
申请号：US12747086
申请日：2010-06-01
申请人： Masahiro Arai , Hiroshi Hirayama , Masanori Takada , Hiroshi Kanayama , Hideaki Fukuda
发明人： Masahiro Arai , Hiroshi Hirayama , Masanori Takada , Hiroshi Kanayama , Hideaki Fukuda
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C7/10 , G06F13/28 , G06F13/4282 , G06F2213/0026
摘要： A data transfer device that confirms completion of writing into a memory on transferring data to the memory via a bus through which a response indicating completion of data writing in the memory is not sent back includes an inter-memory data transfer control unit performing data transfer between the memories. When the inter-memory data transfer control unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by a procedure different from writing into the memory. When a data transfer with a designated transfer length is completed, in order to confirm that writing is completed as to the write destination memory at the end of the data transfer, the inter-memory data transfer control unit performs confirmation of write completion as to the write destination memory at the end of the transfer by the procedure different from writing into the memory. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of write completion.
摘要翻译：一种数据传送装置，其确认写入到存储器中的写入数据经由经由总线的数据传送到存储器，通过该总线不指示在存储器中写入数据的响应的响应不被发回包括存储器间数据传送控制单元，回忆当存储器间数据传送控制单元检测从第一存储器到第二存储器的写入目的地存储器的切换时，为了确认对第一存储器的写入完成，存储器间数据传送控制单元执行写入的确认通过不同于写入内存的过程来完成第一个内存。当具有指定传送长度的数据传输完成时，为了确认在数据传送结束时关于写入目的地存储器的写入完成，存储器间数据传送控制单元执行关于写入完成的确认通过与写入存储器不同的过程在传送结束时写入目标存储器。存储器间数据传送控制单元基于写入完成的确认通知处理器完成存储器间数据传送。

10. 发明授权

US08901016B2 Method of forming metal oxide hardmask 有权
标题翻译：形成金属氧化物硬掩模的方法
公开(公告)号：US08901016B2
公开(公告)日：2014-12-02
申请号：US13333420
申请日：2011-12-21
申请人： Jeongseok Ha , Hideaki Fukuda , Shintaro Kaido
发明人： Jeongseok Ha , Hideaki Fukuda , Shintaro Kaido
IPC分类号： H01L21/228 , H01L21/02 , H01L21/033
CPC分类号： H01L21/02153 , G03F1/00 , H01L21/0215 , H01L21/02186 , H01L21/02274 , H01L21/0228 , H01L21/0337
摘要： A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula SixM(1-x)Oy wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.
摘要翻译：在模板上形成金属氧化物硬掩模的方法包括：提供由形成在基板上的光致抗蚀剂或无定形碳构成的模板; 并通过原子层沉积（ALD）在由具有式SixM（1-x）Oy的材料构成的模板上沉积金属氧化物硬掩模，其中M表示至少一种金属元素，x小于包括0的一个，y是约两个或化学计量确定的数目。

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