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1. 发明授权

US08321622B2 Storage system with multiple controllers and multiple processing paths 有权
标题翻译：具有多个控制器和多个处理路径的存储系统
公开(公告)号：US08321622B2
公开(公告)日：2012-11-27
申请号：US12668721
申请日：2009-11-10
申请人： Shuji Nakamura , Emi Nakamura, legal representative , Masahiro Arai , Hideaki Fukuda , Nobuyuki Minowa
发明人： Shuji Nakamura , Masahiro Arai , Hideaki Fukuda , Nobuyuki Minowa
IPC分类号： H04L12/50
CPC分类号： G06F12/0813 , G06F12/0868 , G06F2212/284 , G06F2212/286
摘要： The first controller includes a first relay circuit which is a circuit that controls data transfer, and a first processor coupled to the first relay circuit via a first second path. The second controller includes a second relay circuit which is a circuit that controls data transfer, and is coupled to the first relay circuit via the first path, and a second processor coupled to the second relay circuit via a second second path. The first processor is coupled to the second relay circuit not via the first relay circuit but via a first third path, and accesses the second relay circuit via the first third path during an I/O process. The second processor is coupled to the first relay circuit not via the second relay circuit but via a second third path, and accesses the first relay circuit via the second third path during an I/O process.
摘要翻译：第一控制器包括作为控制数据传输的电路的第一继电器电路和经由第一第二路径耦合到第一继电器电路的第一处理器。第二控制器包括第二继电器电路，其是控制数据传输并且经由第一路径耦合到第一继电器电路的电路，以及经由第二第二路径耦合到第二继电器电路的第二处理器。第一处理器不是经由第一继电器电路而是经由第一第三路径耦合到第二继电器电路，并且在I / O过程期间经由第一第三路径访问第二继电器电路。第二处理器不经由第二继电器电路而经由第二第三路径耦合到第一继电器电路，并且在I / O过程期间经由第二第三路径访问第一继电器电路。

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