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1. 发明申请

US20070222032A1 Bipolar transistor and method for producing a bipolar transistor 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：US20070222032A1
公开(公告)日：2007-09-27
申请号：US11716526
申请日：2007-03-09
申请人： Herbert Schaefer , Josef Boeck , Rudolf Lachner , Thomas Meister
发明人： Herbert Schaefer , Josef Boeck , Rudolf Lachner , Thomas Meister
IPC分类号： H01L27/082
CPC分类号： H01L29/7378 , H01L29/0804 , H01L29/66242 , H01L29/66287 , H01L29/732
摘要： A bipolar transistor has a base, an emitter and an emitter contact. The emitter has a monocrystalline layer and a polycrystalline layer, which are disposed between the base and the emitter contact in the mentioned order.
摘要翻译：双极晶体管具有基极，发射极和发射极接触。发射极具有单晶层和多晶层，它们以所述顺序设置在基极和发射极之间。

2. 发明授权

US08329532B2 Process for the simultaneous deposition of crystalline and amorphous layers with doping 有权
公开(公告)号：US08329532B2
公开(公告)日：2012-12-11
申请号：US13314595
申请日：2011-12-08
申请人： Herbert Schaefer , Martin Franosch , Thomas Meister , Josef Boeck
发明人： Herbert Schaefer , Martin Franosch , Thomas Meister , Josef Boeck
IPC分类号： H01L21/8238
CPC分类号： H01L21/02639 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02661
摘要： One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.

3. 发明授权

US08067290B2 Bipolar transistor with base-collector-isolation without dielectric 有权
标题翻译：双极晶体管，具有基极集电绝缘无绝缘
公开(公告)号：US08067290B2
公开(公告)日：2011-11-29
申请号：US12642188
申请日：2009-12-18
申请人： Josef Boeck , Wolfgang Liebl , Thomas Meister , Herbert Schaefer
发明人： Josef Boeck , Wolfgang Liebl , Thomas Meister , Herbert Schaefer
IPC分类号： H01L21/331
CPC分类号： H01L29/7322 , H01L29/0649 , H01L29/0821 , H01L29/66272
摘要： The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittivity gas. In particular, a multilayer base-collector dielectric film is deposited over the collector region. A base region is formed onto the multilayer dielectric film and is patterned to form one or more base connection regions. The multilayer dielectric film is selectively etched during a plurality of isotropic etch processes to allow for the formation of one or more isolation region between the base connection regions and the collector region, wherein the one or more isolation regions comprise cavities filled with a gas having a low dielectric constant (e.g., air). The resultant bipolar transistor has a reduced base-collector capacitance, thereby allowing for improved frequency properties (e.g., higher maximum frequency operation).
摘要翻译：所公开的发明提供了一种用于制造双极晶体管的方法，该双极晶体管具有包含在通过一个或多个填充有低介电常数气体的隔离空腔（例如，气隙）与上覆基极区域分离的半导体主体内的集电极区域。特别地，在集电极区域上沉积多层基极集电极电介质膜。在多层电介质膜上形成基极区，并形成一个或多个基极连接区域。在多个各向同性蚀刻工艺期间选择性地蚀刻多层电介质膜，以允许在基底连接区域和收集区域之间形成一个或多个隔离区域，其中一个或多个隔离区域包括填充有具有低介电常数（如空气）。所得的双极晶体管具有降低的基极 - 集电极电容，从而允许改进的频率特性（例如，较高的最大频率运行）。

4. 发明申请

US20100187657A1 BIPOLAR TRANSISTOR WITH BASE-COLLECTOR-ISOLATION WITHOUT DIELECTRIC 有权
标题翻译：具有无电介质的基础收集器隔离的双极晶体管
公开(公告)号：US20100187657A1
公开(公告)日：2010-07-29
申请号：US12642188
申请日：2009-12-18
申请人： Josef Boeck , Wolfgang Liebl , Thomas Meister , Herbert Schaefer
发明人： Josef Boeck , Wolfgang Liebl , Thomas Meister , Herbert Schaefer
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/7322 , H01L29/0649 , H01L29/0821 , H01L29/66272
摘要： The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittivity gas. In particular, a multilayer base-collector dielectric film is deposited over the collector region. A base region is formed onto the multilayer dielectric film and is patterned to form one or more base connection regions. The multilayer dielectric film is selectively etched during a plurality of isotropic etch processes to allow for the formation of one or more isolation region between the base connection regions and the collector region, wherein the one or more isolation regions comprise cavities filled with a gas having a low dielectric constant (e.g., air). The resultant bipolar transistor has a reduced base-collector capacitance, thereby allowing for improved frequency properties (e.g., higher maximum frequency operation).
摘要翻译：所公开的发明提供了一种用于制造双极晶体管的方法，该双极晶体管具有包含在通过一个或多个填充有低介电常数气体的隔离空腔（例如，气隙）与上覆基极区域分离的半导体主体内的集电极区域。特别地，在集电极区域上沉积多层基极集电极电介质膜。在多层电介质膜上形成基极区，并形成一个或多个基极连接区域。在多个各向同性蚀刻工艺期间选择性地蚀刻多层电介质膜，以允许在基底连接区域和收集区域之间形成一个或多个隔离区域，其中一个或多个隔离区域包括填充有具有低介电常数（如空气）。所得的双极晶体管具有降低的基极 - 集电极电容，从而允许改进的频率特性（例如，更高的最大频率运行）。

5. 发明申请

US20090261327A1 PROCESS FOR THE SIMULTANEOUS DEPOSITION OF CRYSTALLINE AND AMORPHOUS LAYERS WITH DOPING 有权
标题翻译：晶体和非晶层同时沉积的方法
公开(公告)号：US20090261327A1
公开(公告)日：2009-10-22
申请号：US12106667
申请日：2008-04-21
申请人： Herbert Schaefer , Martin Franosch , Thomas Meister , Josef Boeck
发明人： Herbert Schaefer , Martin Franosch , Thomas Meister , Josef Boeck
IPC分类号： H01L27/00 , H01L21/62
CPC分类号： H01L21/02639 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02661
摘要： One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
摘要翻译：本发明的一个实施例涉及利用原位差分外延在半导体主体上同时沉积多个不同结晶结构的方法。在本发明的一个实施方案中，形成制备表面，得到两个不同的结晶区域，单晶硅衬底区域和隔离层区域。单晶硅层和非晶硅层同时直接分布在单晶硅衬底区域和隔离层区域的制备表面上。沉积包括形成两个或更多个子层。可以为每个单独的子层改变工艺参数以优化沉积特性。

6. 发明授权

US07449389B2 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US07449389B2
公开(公告)日：2008-11-11
申请号：US11553704
申请日：2006-10-27
申请人： Thomas Meister , Herbert Schäfer , Josef Böck , Rudolf Lachner
发明人： Thomas Meister , Herbert Schäfer , Josef Böck , Rudolf Lachner
IPC分类号： H01L21/20
CPC分类号： H01L21/8249 , H01L27/0635 , H01L27/0658 , H01L29/66242 , H01L29/7378 , H01L29/93
摘要： A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.
摘要翻译：提供了一种制造半导体的方法，包括在半导体本体中限定第一分量区域和第二分量区域。通过第一分量区域形成第一外延层。第二外延层形成在第一外延层上方，包括经由第一外延层和第二外延层，与第二成分区的第二有源区独立地配置第一成分区的第一有源区的物理尺寸。在一个实施例中，第一部件是射频晶体管，第二部件是变容二极管。

7. 发明申请

US20080227261A1 METHOD FOR FABRICATING A TRANSISTOR STRUCTURE 有权
标题翻译：制造晶体管结构的方法
公开(公告)号：US20080227261A1
公开(公告)日：2008-09-18
申请号：US12051928
申请日：2008-03-20
申请人： Josef Bock , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schafer , Martin Seck
发明人： Josef Bock , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schafer , Martin Seck
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L21/8222 , H01L27/0825 , H01L29/0821
摘要： The invention relates to a method for fabricating a transistor structure, comprising at least a first and a second bipolar transistor having different collector widths.The invention is distinguished by the fact that all junctions between differently doped regions have a sharp interface. In this case, by way of example, a first collector region 2.1 is suitable for a high-frequency transistor with high limiting frequencies fT and a second collector region 2.2 is suitable for a high-voltage transistor with increased breakdown voltages.
摘要翻译：本发明涉及一种用于制造晶体管结构的方法，该方法至少包括具有不同集电极宽度的第一和第二双极晶体管。本发明的区别在于，不同掺杂区域之间的所有结点都具有尖锐的界面。在这种情况下，作为示例，第一集电极区域2.1适用于具有高限制频率f T T的高频晶体管，并且第二集电极区域2.2适用于具有增加击穿电压。

8. 发明申请

US20080102593A1 METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20080102593A1
公开(公告)日：2008-05-01
申请号：US11553704
申请日：2006-10-27
申请人： Thomas Meister , Herbert Schafer , Josef Bock , Rudolf Lachner
发明人： Thomas Meister , Herbert Schafer , Josef Bock , Rudolf Lachner
IPC分类号： H01L21/20 , H01L29/70 , H01L31/11 , H01L27/102 , H01L27/082 , H01L21/8222
CPC分类号： H01L21/8249 , H01L27/0635 , H01L27/0658 , H01L29/66242 , H01L29/7378 , H01L29/93
摘要： A method for fabricating a semiconductor including defining a first component region and a second component region in a semiconductor body is provided. A first epitaxial layer is formed through the first component region. A second epitaxial layer is formed over the first epitaxial layer, including configuring the physical dimensions of a first active zone of the first component region independent of a second active zone of the second component region via the first epitaxial layer and the second epitaxial layer. In one embodiment, the first component is a radio-frequency transistor and the second component is a varactor.
摘要翻译：提供了一种制造半导体的方法，包括在半导体本体中限定第一分量区域和第二分量区域。通过第一分量区域形成第一外延层。第二外延层形成在第一外延层上方，包括经由第一外延层和第二外延层，与第二成分区的第二有源区独立地配置第一成分区的第一有源区的物理尺寸。在一个实施例中，第一部件是射频晶体管，第二部件是变容二极管。

9. 发明授权

US07371650B2 Method for producing a transistor structure 有权
标题翻译：晶体管结构的制造方法
公开(公告)号：US07371650B2
公开(公告)日：2008-05-13
申请号：US10532894
申请日：2003-10-24
申请人： Josef Böck , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schäfer , Martin Seck
发明人： Josef Böck , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schäfer , Martin Seck
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L21/8222 , H01L27/0825 , H01L29/0821
摘要： A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.
摘要翻译：提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域层和在第二掩埋层上具有第二集电极宽度的第二集电极区。在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。在第一收集器区域上产生具有第二厚度的第二收集器区域。产生至少一个绝缘区域，其至少隔离收集器区域彼此。

10. 发明申请

US20060009002A1 Method for producing a transistor structure 有权
标题翻译：晶体管结构的制造方法
公开(公告)号：US20060009002A1
公开(公告)日：2006-01-12
申请号：US10532894
申请日：2003-10-24
申请人： Josef Bock , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schafer , Martin Seck
发明人： Josef Bock , Rudolf Lachner , Thomas Meister , Reinhard Stengl , Herbert Schafer , Martin Seck
IPC分类号： H01L21/331 , H01L21/8228
CPC分类号： H01L29/66272 , H01L21/8222 , H01L27/0825 , H01L29/0821
摘要： A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.
摘要翻译：提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域层和在第二掩埋层上具有第二集电极宽度的第二集电极区。在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。在第一收集器区域上产生具有第二厚度的第二收集器区域。产生至少一个绝缘区域，其至少隔离收集器区域彼此。

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