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1. 发明授权

US5457345A Metallization composite having nickle intermediate/interface 失效
标题翻译：金属化复合材料具有中间/界面
公开(公告)号：US5457345A
公开(公告)日：1995-10-10
申请号：US182310
申请日：1994-01-14
申请人： Herbert C. Cook , Paul A. Farrar, Sr. , Robert M. Geffken , William T. Motsiff , Adolf E. Wirsing
发明人： Herbert C. Cook , Paul A. Farrar, Sr. , Robert M. Geffken , William T. Motsiff , Adolf E. Wirsing
IPC分类号： H01L21/28 , H01L21/60 , H01L23/485 , H01L29/45 , H01L23/48 , H01L29/46 , H01L29/54 , H01L29/62
CPC分类号： H01L24/11 , H01L24/13 , H01L29/456 , H01L2224/13113 , H01L2224/13116 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01046 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014
摘要： A metallization composite comprises a refractory metal, nickel, and copper. The refractory metal is preferably titanium (Ti), but other suitable refractory metals such as zirconium and hafnium can also be utilized. An additional optional layer of gold can overlie the copper. The metallization composite is used to connect a solder contact to a semiconductor substrate.
摘要翻译：金属化复合材料包括难熔金属，镍和铜。难熔金属优选为钛（Ti），但也可以使用其它合适的难熔金属如锆和铪。另外一个可选的金层可以覆盖铜。金属化复合材料用于将焊料接触件连接到半导体衬底。

2. 发明授权

US5126006A Plural level chip masking 失效
标题翻译：多级芯片屏蔽
公开(公告)号：US5126006A
公开(公告)日：1992-06-30
申请号：US708608
申请日：1991-05-31
申请人： John E. Cronin , Paul A. Farrar, Sr. , Robert M. Geffken , William H. Guthrie , Carter W. Kaanta , Rosemary A. Previti-Kelly , James G. Ryan , Ronald R. Uttecht , Andrew J. Watts
发明人： John E. Cronin , Paul A. Farrar, Sr. , Robert M. Geffken , William H. Guthrie , Carter W. Kaanta , Rosemary A. Previti-Kelly , James G. Ryan , Ronald R. Uttecht , Andrew J. Watts
IPC分类号： G03F1/00 , G03F7/00
CPC分类号： G03F7/0035 , G03F1/50
摘要： A sequence of masking steps reduces the amount of transference of a workpiece among work stations and reduces certain tolerances required for mask alignment in the construction of integrated circuits, and a gray level mask suitable for photolithography. In the integrated circuit, masking layers are developed directly in a wafer for delineating vertical and horizontal portions of an electrically conductive path. The mask is constructed of a transparent glass substrate which supports plural levels of materials having different optical transmissivities. In the case of a mask employing only two of these levels, one level may be constructed of a glass made partially transmissive by substitution of silver ions in place of metal ions of alkali metal silicates employed in the construction of the glass. The second layer may be made opaque by construction of the layer of a metal such as chromium. Both the wafer and the mask are fabricated by a photoresist structure which is etched in specific regions by photolithographic masking to enable selective etching of exposed regions of the level of materials of differing optical transmissivities. Various etches are employed for selective etching of the photoresist and other ones of the layers. The etches include plasma etch with chloride ions to attack the chromium of the opaque layer, compounds of fluorine to attack the glass layer, and reactive ion etching with oxygen to attack the photoresist structure.
摘要翻译：一系列掩蔽步骤减少了工件之间工件的移动量，并降低了集成电路结构中掩模对准所需的某些公差以及适用于光刻的灰度级掩模。在集成电路中，掩模层直接在晶片中显影，用于描绘导电路径的垂直和水平部分。掩模由透明玻璃基板构成，其支撑具有不同透光率的多层材料。在仅使用这些水平中的两个的掩模的情况下，一个层可以由通过取代银离子代替在玻璃的结构中使用的碱金属硅酸盐的金属离子而部分透射的玻璃构成。第二层可以通过金属如铬的构造而变得不透明。晶片和掩模都通过光致抗蚀剂结构制造，该光致抗蚀剂结构通过光刻掩模在特定区域中被蚀刻，以使得能够选择性地蚀刻具有不同光学透射率的材料层的暴露区域。各种蚀刻用于选择性蚀刻光致抗蚀剂和其它层。蚀刻包括用氯离子等离子体蚀刻以侵蚀不透明层的铬，氟的化合物侵蚀玻璃层，以及用氧反应离子蚀刻以侵蚀光致抗蚀剂结构。

3. 发明授权

US07071532B2 Adjustable self-aligned air gap dielectric for low capacitance wiring 有权
公开(公告)号：US07071532B2
公开(公告)日：2006-07-04
申请号：US10605440
申请日：2003-09-30
申请人： Robert M. Geffken , William T. Motsiff
发明人： Robert M. Geffken , William T. Motsiff
IPC分类号： H01L29/00
CPC分类号： H01L21/76831 , H01L21/76811 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed between the first and second interconnects. The air gap extends above an upper surface of at least one of the first and second interconnects and below a lower surface of at least one of the first and second interconnects, and the distance between the spacers defines the width of the air gap. The air gap is self-aligned to the adjacent sides of the first and second interconnects.

4. 发明授权

US06498385B1 Post-fuse blow corrosion prevention structure for copper fuses 有权
标题翻译：铜熔丝保险丝熔断防腐结构
公开(公告)号：US06498385B1
公开(公告)日：2002-12-24
申请号：US09388314
申请日：1999-09-01
申请人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
发明人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/76843 , H01L23/5258 , H01L28/20 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.
摘要翻译：公开了一种制造半导体耐腐蚀金属熔丝线的结构和方法，其包括也可以用作电阻器的耐火衬垫。使用镶嵌工艺完成制作。金属结构可以形成在包括包括第一层和第二层的第一部分的半导体衬底上，第一层具有比第二层更高的电阻率，第二层具有与第一层接触的水平和垂直表面在第一部分中，以及第二部分，其联接到第一部分，第二部分由第一层组成，第一层不与第二部分中的第二层的水平和垂直表面接触。金属结构可用作耐腐蚀保险丝。金属结构也可以用作电阻元件。高耐压电阻器结构允许在混合电压，混合信号和模拟/数字应用中使用。电阻元件具有低电容，低效果，高线性度，高熔点温度和高临界电流故障。电阻器结构可以形成在电介质槽的壁上。该结构可以应用于诸如ESD网络，RC耦合MOSFET，电阻器镇流MOSFET等电路应用。电阻可以与MOSFET或其他结构串联。

5. 发明授权

US07358148B2 Adjustable self-aligned air gap dielectric for low capacitance wiring 有权
标题翻译：可调式自对准气隙电介质用于低电容布线
公开(公告)号：US07358148B2
公开(公告)日：2008-04-15
申请号：US11418921
申请日：2006-05-05
申请人： Robert M. Geffken , William T. Motsiff
发明人： Robert M. Geffken , William T. Motsiff
IPC分类号： H01L21/76
CPC分类号： H01L21/76831 , H01L21/76811 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed between the first and second interconnects. The air gap extends above an upper surface of at least one of the first and second interconnects and below a lower surface of at least one of the first and second interconnects, and the distance between the spacers defines the width of the air gap. The air gap is self-aligned to the adjacent sides of the first and second interconnects.
摘要翻译：可调整的自对准低电容集成电路气隙结构包括邻近互连层上的第二互连的第一互连，沿着第一和第二互连的相邻侧形成的隔离物，以及形成在第一和第二互连之间的气隙。空气间隙在第一和第二互连中的至少一个的上表面上方延伸并且在第一和第二互连中的至少一个互连的下表面之下，并且间隔件之间的距离限定气隙的宽度。气隙与第一和第二互连的相邻侧自对准。

6. 发明授权

US06982227B2 Single and multilevel rework 失效
标题翻译：单层和多层返工
公开(公告)号：US06982227B2
公开(公告)日：2006-01-03
申请号：US10687294
申请日：2003-10-16
申请人： Edward C. Cooney, III , Robert M. Geffken , Vincent J. McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
发明人： Edward C. Cooney, III , Robert M. Geffken , Vincent J. McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
IPC分类号： H01L21/302
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76807 , H01L21/76892 , H01L23/525 , H01L23/5329 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.
摘要翻译：一种重新加工BEOL（处理线的后端）金刚石冶金的金属化水平的方法包括在衬底上形成多个BEOL金属化水平，在BEOL金属化水平中形成线和通孔部分，选择性地去除BEOL金属化中的至少一个以暴露线路和通孔部分，并且用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平，其中BEOL金属化水平包括第一介电层和第二介电层，并且其中第一介电层包括下部介电常数材料比第二介电层。

7. 发明授权

US06746947B2 Post-fuse blow corrosion prevention structure for copper fuses 有权
标题翻译：铜熔丝保险丝熔断防腐结构
公开(公告)号：US06746947B2
公开(公告)日：2004-06-08
申请号：US10254277
申请日：2002-09-25
申请人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
发明人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L2144
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/76843 , H01L23/5258 , H01L28/20 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.
摘要翻译：公开了一种制造半导体耐腐蚀金属熔丝线的结构和方法，其包括也可以用作电阻器的耐火衬垫。使用镶嵌工艺完成制作。金属结构可以形成在包括包括第一层和第二层的第一部分的半导体衬底上，第一层具有比第二层更高的电阻率，第二层具有与第一层接触的水平和垂直表面在第一部分中，以及第二部分，其联接到第一部分，第二部分由第一层组成，第一层不与第二部分中的第二层的水平和垂直表面接触。金属结构可用作耐腐蚀保险丝。金属结构也可以用作电阻元件。高耐压电阻器结构允许在混合电压，混合信号和模拟/数字应用中使用。电阻元件具有低电容，低效果，高线性度，高熔点温度和高临界电流故障。电阻器结构可以形成在电介质槽的壁上。该结构可以应用于诸如ESD网络，RC耦合MOSFET，电阻器镇流MOSFET等电路应用。电阻可以与MOSFET或其他结构串联。

8. 发明授权

US06344373B1 Antifuse structure and process 失效
标题翻译：形成反熔丝的方法
公开(公告)号：US06344373B1
公开(公告)日：2002-02-05
申请号：US09106980
申请日：1998-06-29
申请人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译：根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。两层芯优选包括注入层和电介质层。注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。最初，喷射器层和电介质层是不导电的。当施加足够的电压时，芯保持在一起并变得导电。

9. 发明授权

US5811870A Antifuse structure 失效
标题翻译：防腐结构
公开(公告)号：US5811870A
公开(公告)日：1998-09-22
申请号：US850033
申请日：1997-05-02
申请人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
发明人： Arup Bhattacharyya , Robert M. Geffken , Chung H. Lam , Robert K. Leidy
IPC分类号： H01L21/82 , H01L23/525 , H01L29/04
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： According to the preferred embodiment, an antifuse structure and method for personalizing a semiconductor device is provided that overcomes the limitations of the prior art. The preferred embodiment antifuse comprises a two layer transformable insulator core between two electrodes. The transformable core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes. The two layer core preferably comprises an injector layer and a dielectric layer. The injector layer preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer and dielectric layer are non-conductive. When a sufficient voltage is applied the core fuses together and becomes conductive.
摘要翻译：根据优选实施例，提供了克服现有技术限制的用于个性化半导体器件的反熔丝结构和方法。优选的实施例反熔丝包括在两个电极之间的两层可变形的绝缘体芯。可变形的芯通常是非导电的，但是可以通过在电极之间提供足够的电压而将其转变成导电材料。两层芯优选包括注入层和电介质层。注射器层优选地包括两相材料，例如富氮的氮化物或富硅氧化物。最初，喷射器层和电介质层是不导电的。当施加足够的电压时，芯保持在一起并变得导电。

10. 发明申请

US20080203579A1 SACRIFICIAL METAL SPACER DUAL DAMASCENE 审中-公开
公开(公告)号：US20080203579A1
公开(公告)日：2008-08-28
申请号：US12116490
申请日：2008-05-07
申请人： Edward C. Cooney , Robert M. Geffken , Anthony K. Stamper
发明人： Edward C. Cooney , Robert M. Geffken , Anthony K. Stamper
IPC分类号： H01L23/522
CPC分类号： H01L21/76844 , H01L21/76811 , H01L21/76813
摘要： A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.
摘要翻译：用于双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上方形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽，从而产生牺牲钨在槽中的侧壁间隔物，图案化叠层绝缘体堆叠，去除牺牲侧壁间隔物，在图案化的层压绝缘体堆叠中形成通孔，以及将金属衬垫和导电材料沉积到通孔和槽中，其中层压绝缘体堆叠包括介电层还包含氧化物和聚亚芳基。沉积步骤防止层压的绝缘体叠层溅射到通孔中。此外，沉积步骤包括清洁通孔和槽，可选地执行反应离子蚀刻或氩溅射清洗，在通孔和槽上沉积多个金属层，以及在通孔和槽中沉积铜。

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