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1. 发明授权

US07105099B2 Method of reducing pattern pitch in integrated circuits 有权
标题翻译：降低集成电路中图案间距的方法
公开(公告)号：US07105099B2
公开(公告)日：2006-09-12
申请号：US10710488
申请日：2004-07-14
申请人： Henry Chung , Ming-Chung Liang , An-Chi Wei , Shin-Yi Tsai , Kuo-Liang Wei
发明人： Henry Chung , Ming-Chung Liang , An-Chi Wei , Shin-Yi Tsai , Kuo-Liang Wei
IPC分类号： B44C1/22 , H01L21/00
CPC分类号： H01L21/31116 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32136 , H01L21/32139 , Y10S438/947
摘要： A method of reducing pattern pitch is provided. A material layer, a hard mask layer and a patterned photoresist layer are sequentially formed over a substrate. Using the patterned photoresist layer as etching mask, the hard mask layer is etched. Due to the trenching effect, a residual hard mask layer remains in an exposed region exposed by the photoresist layer and micro-trenches are formed at the edges of the residual hard mask layer. Thereafter, using the residual hard mask layer as etching mask to pattern the material layer. Finally, the patterned photoresist layer and the hard mask layer are removed. In the invention, the trenching effect is utilized when etching the hard mask layer. A portion of the hard mask layer remains, and the micro-trenches are formed in the hard mask layer. After the micro-trenches are transferred to the material layer, the pattern pitch can be reduced.
摘要翻译：提供了一种降低图形间距的方法。在衬底上顺序地形成材料层，硬掩模层和图案化的光致抗蚀剂层。使用图案化的光致抗蚀剂层作为蚀刻掩模，蚀刻硬掩模层。由于挖沟效应，残留的硬掩模层保留在由光致抗蚀剂层暴露的暴露区域中，并且在残留硬掩模层的边缘处形成微沟槽。此后，使用残留的硬掩模层作为蚀刻掩模来图案化材料层。最后，去除图案化的光致抗蚀剂层和硬掩模层。在本发明中，当蚀刻硬掩模层时，利用挖沟效应。硬掩模层的一部分残留，并且微沟槽形成在硬掩模层中。在将微沟槽转移到材料层之后，可以减小图案间距。

2. 发明申请

US20060011575A1 [METHOD OF REDUCING PATTERN PITCH IN INTEGRATED CIRCUITS] 有权
标题翻译： [集成电路中减少图案的方法]
公开(公告)号：US20060011575A1
公开(公告)日：2006-01-19
申请号：US10710488
申请日：2004-07-14
申请人： Henry Chung , Ming-Chung Liang , An-Chi Wei , Shin-Yi Tsai , Kuo-Liang Wei
发明人： Henry Chung , Ming-Chung Liang , An-Chi Wei , Shin-Yi Tsai , Kuo-Liang Wei
IPC分类号： B44C1/22 , H01L21/302
CPC分类号： H01L21/31116 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32136 , H01L21/32139 , Y10S438/947
摘要： A method of reducing pattern pitch is provided. A material layer, a hard mask layer and a patterned photoresist layer are sequentially formed over a substrate. Using the patterned photoresist layer as etching mask, the hard mask layer is etched. Due to the trenching effect, a residual hard mask layer remains in an exposed region exposed by the photoresist layer and micro-trenches are formed at the edges of the residual hard mask layer. Thereafter, using the residual hard mask layer as etching mask to pattern the material layer. Finally, the patterned photoresist layer and the hard mask layer are removed. In the invention, the trenching effect is utilized when etching the hard mask layer. A portion of the hard mask layer remains, and the micro-trenches are formed in the hard mask layer. After the micro-trenches are transferred to the material layer, the pattern pitch can be reduced.
摘要翻译：提供了一种降低图形间距的方法。在衬底上顺序地形成材料层，硬掩模层和图案化的光致抗蚀剂层。使用图案化的光致抗蚀剂层作为蚀刻掩模，蚀刻硬掩模层。由于挖沟效应，残留的硬掩模层保留在由光致抗蚀剂层暴露的暴露区域中，并且在残留硬掩模层的边缘处形成微沟槽。此后，使用残留的硬掩模层作为蚀刻掩模来图案化材料层。最后，去除图案化的光致抗蚀剂层和硬掩模层。在本发明中，当蚀刻硬掩模层时，利用挖沟效应。硬掩模层的一部分残留，并且微沟槽形成在硬掩模层中。在将微沟槽转移到材料层之后，可以减小图案间距。

3. 发明授权

US06750150B2 Method for reducing dimensions between patterns on a photoresist 有权
公开(公告)号：US06750150B2
公开(公告)日：2004-06-15
申请号：US09978546
申请日：2001-10-18
申请人： Henry Wei-Ming Chung , Shin-Yi Tsai , Ming-Chung Liang
发明人： Henry Wei-Ming Chung , Shin-Yi Tsai , Ming-Chung Liang
IPC分类号： H01L211302
CPC分类号： H01L21/0274 , G03F7/405 , H01L21/0332 , H01L21/0335 , H01L21/0338 , Y10S438/947 , Y10S438/951
摘要： A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

4. 发明授权

US06511902B1 Fabrication method for forming rounded corner of contact window and via by two-step light etching technique 有权
标题翻译：通过两步光蚀刻技术形成接触窗和通孔的圆角的制造方法
公开(公告)号：US06511902B1
公开(公告)日：2003-01-28
申请号：US10105266
申请日：2002-03-26
申请人： Ming-Chung Liang , Shin-Yi Tsai
发明人： Ming-Chung Liang , Shin-Yi Tsai
IPC分类号： H01L214763
CPC分类号： H01L21/76804 , H01L21/31116
摘要： The present invention generally relates to provide a fabrication method for forming a rounded corner of a contact window or a via by using a two-step light etching technique. In the present invention, after the etching process to form the contact window or the via, an object of the invention is to utilize oxygen plasma and fluorocarbon plasma of the two-step light etching technique to produce the rounded corner of the window or via so as this rounded opening profile of the contact window or the via can supply for following metal-filling processes.
摘要翻译：本发明一般涉及通过使用两步光蚀刻技术来形成接触窗或通孔的圆角的制造方法。在本发明中，在形成接触窗或通孔的蚀刻工艺之后，本发明的目的是利用两步光蚀刻技术的氧等离子体和氟碳等离子体来产生窗口的圆角或通孔因为接触窗口或通孔的圆形开口轮廓可以供应用于以下金属填充过程。

5. 发明授权

US07303995B2 Method for reducing dimensions between patterns on a photoresist 有权
标题翻译：降低光致抗蚀剂图案之间尺寸的方法
公开(公告)号：US07303995B2
公开(公告)日：2007-12-04
申请号：US10465850
申请日：2003-06-20
申请人： Henry Wei-Ming Chung , Shin-Yi Tsai , Ming-Chung Liang
发明人： Henry Wei-Ming Chung , Shin-Yi Tsai , Ming-Chung Liang
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： G03F7/405 , H01L21/0274 , H01L21/0332 , H01L21/0335 , H01L21/0338
摘要： A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of material.
摘要翻译：一种半导体制造方法，其包括提供衬底，在所述衬底上提供材料层，在所述材料层上提供光致抗蚀剂层，图案化和限定所述光致抗蚀剂层，在所述图案化和限定的光致抗蚀剂层上沉积聚合物层，其中聚合物层是共形和不敏感的，并且蚀刻聚合物层和材料层。

6. 发明授权

US06601596B2 Apparatus for cleaning a wafer with shearing stress from slab with curved portion 有权
标题翻译：用于从具有弯曲部分的板坯的剪切应力清洁晶片的装置
公开(公告)号：US06601596B2
公开(公告)日：2003-08-05
申请号：US09847200
申请日：2001-05-02
申请人： Ming-Chung Liang , Shin-Yi Tsai
发明人： Ming-Chung Liang , Shin-Yi Tsai
IPC分类号： B08B300
CPC分类号： B08B3/10
摘要： An apparatus for cleaning a semiconductor wafer is disclosed to substantially improve the efficiency of the cleaning process, and reduce the quantity of cleaning solvent used. The apparatus includes a rotating table for supporting the wafer, a rotation device to rotate the rotation table, a movable or stationary curved-slab for scrubbing the surface of the wafer efficiently, a cleaning nozzle for applying a cleaning solvent or stripper on the surface of the wafer, and a resistance wall for preventing the cleaning solvent spun out from the wafer to pollute the cleaning room.
摘要翻译：公开了一种用于清洁半导体晶片的设备，以显着提高清洁过程的效率，并减少使用的清洗溶剂的量。该装置包括用于支撑晶片的旋转台，用于旋转转台的旋转装置，用于高效洗刷晶片表面的可移动或固定的弯曲板，用于将清洁溶剂或剥离器施加在表面上的清洁喷嘴晶片和用于防止从晶片纺出的清洗溶剂污染清洁室的电阻壁。

7. 发明授权

US07361604B2 Method for reducing dimensions between patterns on a hardmask 有权
标题翻译：减少硬掩模上图案之间尺寸的方法
公开(公告)号：US07361604B2
公开(公告)日：2008-04-22
申请号：US10465852
申请日：2003-06-20
申请人： Henry Wei-Ming Chung , Shin-Yi Tsai , Ming-Chung Liang
发明人： Henry Wei-Ming Chung , Shin-Yi Tsai , Ming-Chung Liang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： G03F7/405 , H01L21/0274 , H01L21/0332 , H01L21/0335 , H01L21/0338
摘要： A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure includes at least one substantially vertical sidewall and one substantially horizontal top, and wherein the hardmask structures are separated by a first space, depositing a photo-insensitive material over the at least two hardmask structures and the first layer, wherein an amount of the photo-insensitive material deposited on the top of the hardmask structures is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the hardmask structures, wherein the hardmask structures with the photo-insensitive layer on the sidewalls thereof are separated by a second space, and wherein the first space is greater than the second space.
摘要翻译：一种半导体制造方法，包括在衬底上沉积第一层，在所述第一层上提供硬掩模层，图案化和限定所述硬掩模层以形成至少两个硬掩模结构，其中每个硬掩模结构包括至少一个基本垂直的侧壁和一个基本上水平的顶部，并且其中所述硬掩模结构由第一空间分开，在所述至少两个硬掩模结构和所述第一层上沉积光敏材料，其中一定量的光敏材料沉积在硬掩模结构基本上大于沉积在硬掩模结构的至少一个侧壁上的不敏感光材料的量，其中在其侧壁上具有光不敏感层的硬掩模结构被第二空间隔开，并且其中第一空间大于第二空间。

8. 发明授权

US07033948B2 Method for reducing dimensions between patterns on a photoresist 有权
公开(公告)号：US07033948B2
公开(公告)日：2006-04-25
申请号：US10739049
申请日：2003-12-19
申请人： Henry Wei-Ming Chung , Shin-Yi Tsai , Ming-Chung Liang
发明人： Henry Wei-Ming Chung , Shin-Yi Tsai , Ming-Chung Liang
IPC分类号： H01L21/302
CPC分类号： H01L21/0274 , G03F7/405 , H01L21/0332 , H01L21/0335 , H01L21/0338 , Y10S438/947 , Y10S438/951
摘要： A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

9. 发明授权

US06635579B2 Operating method of a semiconductor etcher 有权
公开(公告)号：US06635579B2
公开(公告)日：2003-10-21
申请号：US09682556
申请日：2001-09-19
申请人： Ming-Chung Liang , Shin-Yi Tsai , Hsu-Sheng Yu , Chun-Hung Lee
发明人： Ming-Chung Liang , Shin-Yi Tsai , Hsu-Sheng Yu , Chun-Hung Lee
IPC分类号： H01L21302
CPC分类号： H01L21/3065
摘要： An operating method of a semiconductor etcher includes three steps. The first step is to provide a first power for shortening a warm-up time of the etcher. The second step is to provide a second power, which is lower than the first power, to perform an etching process. The third step is to provide a third power, which is between the first and second power, for cleaning the etcher.

10. 发明授权

US06492214B2 Method of fabricating an insulating layer 有权
公开(公告)号：US06492214B2
公开(公告)日：2002-12-10
申请号：US09683649
申请日：2002-01-29
申请人： Chien-Wei Chen , Shin-Yi Tsai , Ming-Chung Liang , Jiun-Ren Lai
发明人： Chien-Wei Chen , Shin-Yi Tsai , Ming-Chung Liang , Jiun-Ren Lai
IPC分类号： H01L21338
CPC分类号： H01L21/28123 , H01L21/76224
摘要： A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.

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