会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • Systems and Methods for Obstructing Magnetic Flux
    • 阻塞磁通的系统和方法
    • US20110133738A1
    • 2011-06-09
    • US12632208
    • 2009-12-07
    • Henry C. AbbinkEdward Kanegsberg
    • Henry C. AbbinkEdward Kanegsberg
    • G01R33/44
    • H05K9/00G01C19/60H05K13/00
    • An aspect of the present invention relates to system and method for substantially obstructing magnetic flux. One aspect of the present invention provides an apparatus for substantially obstructing at least one magnetic flux path between an ambient space and a protected volume. The apparatus includes an inner shield, substantially enclosing the protected volume. The inner shield has at least one inner shield aperture extending therethrough to allow external access to the protected volume. An outer shield substantially encloses the inner shield. The outer shield has at least one outer shield aperture extending therethrough to allow internal access from the ambient space. The apparatus is configured to impede magnetic flux between at least one inner shield aperture and at least one outer shield aperture.
    • 本发明的一个方面涉及用于基本上阻碍磁通量的系统和方法。 本发明的一个方面提供一种用于基本上阻挡环境空间和受保护体积之间的至少一个磁通路径的装置。 该装置包括基本上包围受保护体积的内屏蔽件。 内屏蔽件具有延伸穿过其中的至少一个内屏蔽孔,以允许外部访问受保护的体积。 外屏蔽件基本上包围内屏蔽。 外屏蔽件具有延伸穿过其中的至少一个外屏蔽孔,以允许从环境空间内部通路。 该装置被配置为阻止至少一个内屏蔽孔和至少一个外屏蔽孔之间的磁通量。
    • 4. 发明授权
    • Systems and methods for obstructing magnetic flux while shielding a protected volume
    • 阻挡磁通量同时屏蔽受保护体积的系统和方法
    • US08552725B2
    • 2013-10-08
    • US12632208
    • 2009-12-07
    • Henry C. AbbinkEdward Kanegsberg
    • Henry C. AbbinkEdward Kanegsberg
    • G01C19/60G01R33/20
    • H05K9/00G01C19/60H05K13/00
    • An aspect of the present invention relates to system and method for substantially obstructing magnetic flux. One aspect of the present invention provides an apparatus for substantially obstructing at least one magnetic flux path between an ambient space and a protected volume. The apparatus includes an inner shield, substantially enclosing the protected volume. The inner shield has at least one inner shield aperture extending therethrough to allow external access to the protected volume. An outer shield substantially encloses the inner shield. The outer shield has at least one outer shield aperture extending therethrough to allow internal access from the ambient space. The apparatus is configured to impede magnetic flux between at least one inner shield aperture and at least one outer shield aperture.
    • 本发明的一个方面涉及用于基本上阻碍磁通量的系统和方法。 本发明的一个方面提供一种用于基本上阻挡环境空间和受保护体积之间的至少一个磁通路径的装置。 该装置包括基本上包围受保护体积的内屏蔽件。 内屏蔽件具有延伸穿过其中的至少一个内屏蔽孔,以允许外部访问受保护的体积。 外屏蔽件基本上包围内屏蔽。 外屏蔽件具有延伸穿过其中的至少一个外屏蔽孔,以允许从环境空间内部通路。 该装置被配置为阻止至少一个内屏蔽孔和至少一个外屏蔽孔之间的磁通量。
    • 7. 发明授权
    • Integrated optics chip with reduced thermal errors due to pyroelectric
effects
    • 集成光学芯片,由于热电效应而具有减少的热误差
    • US6044184A
    • 2000-03-28
    • US123955
    • 1998-07-28
    • Kenneth W. ShaferHenry C. AbbinkJohn P. RahnChristine E. GeoslingGregory A. Zimmerman
    • Kenneth W. ShaferHenry C. AbbinkJohn P. RahnChristine E. GeoslingGregory A. Zimmerman
    • H01L33/00G02B6/12G02B6/30G02F1/035H01L31/0232
    • G02F1/035G02F2203/21
    • An integrated optics chip with improved performance when exposed to changing temperature is disclosed. The optic chip or integrated optics chip or MIOC has a top surface, a +Z face and -Z face. The integrated optics chip is formed from a crystal substrate having a high electro-optic coefficient such as Lithium Niobate. For the purpose of orienting the components to the optic chip to be described, the +Z crystal axis extends outward from the +Z face, the Z axis being the axis across which a pyroelectric effect is exhibited. The top surface is orthogonal to the Z axis. An input waveguide on the top surface receives an optical signal from an input port, passes the signal via a waveguide network, to an output waveguide coupling the waveguide network to an output port. A portion of the +Z and -Z faces are coated at least partially with a conductive coating. A conductive path couples the +Z and -Z faces to prevent a charge differential from developing between the +Z and -Z faces due to a change in temperature of the optic chip and the pyroelectric effect.
    • 公开了当暴露于变化的温度时具有改进的性能的集成光学芯片。 光学芯片或集成光学芯片或MIOC具有顶面,+ Z面和-Z面。 集成光学芯片由具有高电光系数的晶体衬底形成,例如铌酸锂。 为了将元件定向到要描述的光学芯片,+ Z晶体轴从+ Z面向外延伸,Z轴是表示热电效应的轴。 顶面与Z轴正交。 顶表面上的输入波导接收来自输入端口的光信号,将信号经由波导网络传递到将波导网络耦合到输出端口的输出波导。 至少部分地用导电涂层涂覆一部分+ Z和-Z面。 导电路径耦合+ Z和-Z面,以防止由于光学芯片的温度变化和热电效应而在+ Z和-Z面之间产生电荷差异。