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1. 发明授权

US06961013B2 Guaranteed monotonic digital to analog converter 有权
公开(公告)号：US06961013B2
公开(公告)日：2005-11-01
申请号：US10916728
申请日：2004-08-12
申请人： Heng-Chih Lin , Chien-Chung Chen , Solti Peng
发明人： Heng-Chih Lin , Chien-Chung Chen , Solti Peng
IPC分类号： H03M1/06 , H03M1/12 , H03M1/66 , H03M1/68
CPC分类号： H03M1/0641 , H03M1/687
摘要： A hybrid Nyquist thermometer and sigma delta digital to analog converter is presented. The digital input signal is divided into most significant bits and least significant bits. The most significant bits are converted to a thermometer code. A thermometer element array is controlled by the thermometer code. A fractional value is calculated from the least significant bits and used to dither the first unexercised array element in order to get finer resolution with guaranteed monotonicity.

2. 发明申请

US20050093729A1 Guaranteed monotonic digital to analog converter 有权
标题翻译：保证单调的数模转换器
公开(公告)号：US20050093729A1
公开(公告)日：2005-05-05
申请号：US10916728
申请日：2004-08-12
申请人： Heng-Chih Lin , Chien-Chung Chen , Solti Peng
发明人： Heng-Chih Lin , Chien-Chung Chen , Solti Peng
IPC分类号： H03M1/06 , H03M1/12 , H03M1/66 , H03M1/68
CPC分类号： H03M1/0641 , H03M1/687
摘要： A hybrid Nyquist thermometer and sigma delta digital to analog converter is presented. The digital input signal is divided into most significant bits and least significant bits. The most significant bits are converted to a thermometer code. A thermometer element array is controlled by the thermometer code. A fractional value is calculated from the least significant bits and used to dither the first unexercised array element in order to get finer resolution with guaranteed monotonicity.
摘要翻译：提出了一种混合奈奎斯特温度计和西格玛delta数模转换器。数字输入信号被分为最高有效位和最低有效位。最高有效位被转换为温度计代码。温度计元件阵列由温度计代码控制。从最低有效位计算分数值，并用于抖动第一个未经排序的数组元素，以获得更精细的分辨率并保证单调性。

3. 发明申请

US20060152288A1 Method and system for amplifying a signal 有权
标题翻译：用于放大信号的方法和系统
公开(公告)号：US20060152288A1
公开(公告)日：2006-07-13
申请号：US11031185
申请日：2005-01-07
申请人： Solti Peng , Chien-Chung Chen , Abdellatif Bellaouar , Heng-Chih Lin
发明人： Solti Peng , Chien-Chung Chen , Abdellatif Bellaouar , Heng-Chih Lin
IPC分类号： H03F1/22
CPC分类号： H03F1/30 , H03F3/189 , H03F2200/18 , H03F2200/456 , H03F2200/72
摘要： According to one embodiment of the invention, an amplifier includes a gate bias circuit operable to generate a gate bias voltage and a common gate amplifier that includes a transistor having a gate biased by an output of the gate bias circuit and also having a source connected to an inductor for providing a path to ground for direct current flowing through the transistor. According to another embodiment of the invention, a method for amplifying a signal by an amplifier includes generating a gate bias voltage indicative of a difference between a reference voltage and an output voltage of the amplifier, biasing the gate of the common-gate amplifier with the gate bias voltage, and blocking, by a passive device, alternating current signals from flowing from the source of the transistor to ground.
摘要翻译：根据本发明的一个实施例，放大器包括栅极偏置电路，其可操作以产生栅极偏置电压和公共栅极放大器，该公共栅极放大器包括具有由栅极偏置电路的输出偏置的栅极的晶体管，并且源极连接到电感器，用于为直流电流流过晶体管提供路径。根据本发明的另一个实施例，一种用于放大放大器的信号的方法包括：生成指示放大器的参考电压和输出电压之间的差异的栅极偏置电压，使公共栅极放大器的栅极偏置栅极偏置电压和被无源器件阻塞从晶体管的源极流到地的交流信号。

4. 发明申请

US20050225464A1 Current switching arrangement for D.A.C. reconstruction filtering 有权
标题翻译：电流开关装置重建过滤
公开(公告)号：US20050225464A1
公开(公告)日：2005-10-13
申请号：US10821576
申请日：2004-04-09
申请人： Heng-Chih Lin , Chien-Chung Chen
发明人： Heng-Chih Lin , Chien-Chung Chen
IPC分类号： H03M1/66 , H03M1/74
CPC分类号： H03M1/0614 , H03M1/662 , H03M1/742
摘要： An arrangement provides a reduced harmonic content output signal that represents a value of a digital input signal. The arrangement includes plural storage devices 301 . . . configured to sample and store the digital input signal at different respective phases of a clock signal. The arrangement also has plural current steering digital-to-analog converters (DACs) 311 . . . configured to receive respective stored digital signals from respective ones of the plural storage devices, and to provide respective currents that represent the received stored digital signals. The arrangement also includes a combining arrangement configured to combine the currents from respective ones of the plural current steering DACs, so as to provide the reduced harmonic content output signal that represents the value of the digital input signal.
摘要翻译：一种布置提供了表示数字输入信号的值的减少谐波含量输出信号。该装置包括多个存储装置301。。。配置成在时钟信号的不同相位采样和存储数字输入信号。该装置还具有多个电流转向数模转换器（DAC）311。。。被配置为从多个存储设备中的相应存储设备接收相应的存储的数字信号，并且提供表示所接收的存储的数字信号的相应电流。该装置还包括组合装置，其被配置为组合来自多个电流导向DAC中的相应电流的电流，以便提供表示数字输入信号的值的减少的谐波含量输出信号。

5. 发明申请

US20050134327A1 High Speed signal level detector 有权
标题翻译：高速信号电平检测器
公开(公告)号：US20050134327A1
公开(公告)日：2005-06-23
申请号：US10743571
申请日：2003-12-22
申请人： Jin-sheng Wang , Heng-Chih Lin , Chien-Chung Chen
发明人： Jin-sheng Wang , Heng-Chih Lin , Chien-Chung Chen
IPC分类号： G01R19/165 , H03K5/153
CPC分类号： G01R19/16557
摘要： A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is capable of achieving the desired high-speed level detection without demanding the substantial power consumption required when using either the averaging technique or a high bandwidth op-amp type comparator.
摘要翻译：高速信号电平检测器采用逆变器的高增益和高带宽进行比较。高速信号电平检测器能够实现期望的高速电平检测，而不需要使用平均技术或高带宽运算放大器型比较器所需的实质功耗。

6. 发明授权

US07098830B2 Current switching arrangement for D.A.C. reconstruction filtering 有权
标题翻译：电流开关装置重建过滤
公开(公告)号：US07098830B2
公开(公告)日：2006-08-29
申请号：US10821576
申请日：2004-04-09
申请人： Heng-Chih Lin , Chien-Chung Chen
发明人： Heng-Chih Lin , Chien-Chung Chen
IPC分类号： H03M1/66 , H03M1/06 , H04B1/10
CPC分类号： H03M1/0614 , H03M1/662 , H03M1/742
摘要： An arrangement provides a reduced harmonic content output signal that represents a value of a digital input signal. The arrangement includes plural storage devices 301 . . . configured to sample and store the digital input signal at different respective phases of a clock signal. The arrangement also has plural current steering digital-to-analog converters (DACs) 311 . . . configured to receive respective stored digital signals from respective ones of the plural storage devices, and to provide respective currents that represent the received stored digital signals. The arrangement also includes a combining arrangement configured to combine the currents from respective ones of the plural current steering DACs, so as to provide the reduced harmonic content output signal that represents the value of the digital input signal.
摘要翻译：一种布置提供了表示数字输入信号的值的减少谐波含量输出信号。该装置包括多个存储装置301。。。配置成在时钟信号的不同相位采样和存储数字输入信号。该装置还具有多个电流转向数模转换器（DAC）311。。。被配置为从多个存储设备中的相应存储设备接收相应的存储的数字信号，并且提供表示所接收的存储的数字信号的相应电流。该装置还包括组合装置，其被配置为组合来自多个电流导向DAC中的相应电流的电流，以便提供表示数字输入信号的值的减少的谐波含量输出信号。

7. 发明申请

US20050093638A1 Methods and apparatus to control frequency offsets in digitally controlled crystal oscillators 审中-公开
标题翻译：控制数字控制晶体振荡器频偏的方法和装置
公开(公告)号：US20050093638A1
公开(公告)日：2005-05-05
申请号：US10966220
申请日：2004-10-15
申请人： Heng-Chih Lin , Chien-Chung Chen , Dirk Leipold
发明人： Heng-Chih Lin , Chien-Chung Chen , Dirk Leipold
IPC分类号： H03B1/00 , H03L1/00 , H03L1/02 , H03L7/00
CPC分类号： H03L1/026 , H03L1/028 , H03L7/00
摘要： Methods and systems of adjusting an oscillator frequency are disclosed. One example method includes reading a temperature associated with an oscillator, reading a first tuning code associated with the temperature from a memory, and tuning the oscillator with the first tuning code. The example method may further include determining a second tuning code, and storing the second tuning code and an indication of the temperature in the memory.
摘要翻译：公开了调整振荡器频率的方法和系统。一个示例性方法包括读取与振荡器相关联的温度，从存储器读取与温度相关联的第一调谐代码，以及用第一调谐代码调谐振荡器。示例性方法还可以包括确定第二调谐代码，以及将第二调谐代码和温度的指示存储在存储器中。

8. 发明授权

US07286019B2 Method and system for amplifying a signal 有权
标题翻译：用于放大信号的方法和系统
公开(公告)号：US07286019B2
公开(公告)日：2007-10-23
申请号：US11031185
申请日：2005-01-07
申请人： Solti Peng , Chien-Chung Chen , Abdellatif Bellaouar , Heng-Chih Lin
发明人： Solti Peng , Chien-Chung Chen , Abdellatif Bellaouar , Heng-Chih Lin
IPC分类号： H03F3/04
CPC分类号： H03F1/30 , H03F3/189 , H03F2200/18 , H03F2200/456 , H03F2200/72
摘要： According to one embodiment of the invention, an amplifier includes a gate bias circuit operable to generate a gate bias voltage and a common gate amplifier that includes a transistor having a gate biased by an output of the gate bias circuit and also having a source connected to an inductor for providing a path to ground for direct current flowing through the transistor. According to another embodiment of the invention, a method for amplifying a signal by an amplifier includes generating a gate bias voltage indicative of a difference between a reference voltage and an output voltage of the amplifier, biasing the gate of the common-gate amplifier with the gate bias voltage, and blocking, by a passive device, alternating current signals from flowing from the source of the transistor to ground.
摘要翻译：根据本发明的一个实施例，放大器包括栅极偏置电路，其可操作以产生栅极偏置电压和公共栅极放大器，该公共栅极放大器包括具有由栅极偏置电路的输出偏置的栅极的晶体管，并且源极连接到电感器，用于为直流电流流过晶体管提供路径。根据本发明的另一个实施例，一种用于放大放大器的信号的方法包括：生成指示放大器的参考电压和输出电压之间的差异的栅极偏置电压，使公共栅极放大器的栅极偏置栅极偏置电压和被无源器件阻塞从晶体管的源极流到地的交流信号。

9. 发明授权

US07034579B2 High-speed signal level detector 有权
标题翻译：高速信号电平检测器
公开(公告)号：US07034579B2
公开(公告)日：2006-04-25
申请号：US10743571
申请日：2003-12-22
申请人： Jin-sheng Wang , Heng-Chih Lin , Chien-Chung Chen
发明人： Jin-sheng Wang , Heng-Chih Lin , Chien-Chung Chen
IPC分类号： H03K5/22
CPC分类号： G01R19/16557
摘要： A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is capable of achieving the desired high-speed level detection without demanding the substantial power consumption required when using either the averaging technique or a high bandwidth op-amp type comparator.
摘要翻译：高速信号电平检测器采用逆变器的高增益和高带宽进行比较。高速信号电平检测器能够实现期望的高速电平检测，而不需要使用平均技术或高带宽运算放大器型比较器所需的实质功耗。

10. 发明申请

US20050280462A1 INVERSE FUNCTION METHOD FOR SEMICONDUCTOR MIXER LINEARITY ENHANCEMENT 有权
标题翻译：用于半导体混合器线性增强的反相函数方法
公开(公告)号：US20050280462A1
公开(公告)日：2005-12-22
申请号：US10869680
申请日：2004-06-16
申请人： Heng-Chih Lin , Chien-Chung Chen , Ranjit Gharpurey
发明人： Heng-Chih Lin , Chien-Chung Chen , Ranjit Gharpurey
IPC分类号： H03D7/14 , H03G3/10
CPC分类号： H03D7/1441 , H03D7/1408 , H03D7/1458 , H03D7/1491
摘要： The mixer circuit includes a differential rf input driver; a differential local oscillator input circuit coupled to the differential rf input driver; a non-linear load coupled to the differential local oscillator input circuit wherein the non-linear load compensates for non-linearity of the differential rf input driver. The non-linear load has a V-I (voltage-current) transfer function the inverse of the input driver. This improves the mixer linearity without sacrificing the Gain or Noise Figure.
摘要翻译：混频器电路包括差分rf输入驱动器; 耦合到差分rf输入驱动器的差分本地振荡器输入电路; 耦合到差分本地振荡器输入电路的非线性负载，其中非线性负载补偿差分rf输入驱动器的非线性。非线性负载具有V-I（电压 - 电流）传递函数，与输入驱动器相反。这可以提高混频器的线性度，而不会牺牲增益或噪声系数。

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