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1. 发明授权

US06605860B1 Semiconductor structures and manufacturing methods 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06605860B1
公开(公告)日：2003-08-12
申请号：US09597442
申请日：2000-06-20
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
IPC分类号： H01L2906
CPC分类号： H01L21/28202 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/02238 , H01L21/02247 , H01L21/02255 , H01L21/2822 , H01L21/3144 , H01L21/31658 , H01L27/10864 , H01L29/045 , H01L29/42368 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/7827 , Y10S257/905
摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of bon axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the with substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.
摘要翻译：一种在硅主体上形成基本上均匀的厚的热生长二氧化硅材料的方法，其独立于凸轮轴。沟槽形成在硅体的表面中，这样的沟槽具有设置在不同结晶平面中的侧壁，这些平面中的一个是100晶体平面，另外一个这样的平面是“10”平面。在侧壁上形成基本均匀的氮化硅层。具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅具有比<110>平面上的厚度大于超过<100>平面的厚度。对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分在氮化硅材料的下面部分上的<110>面上的二氧化硅。选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

2. 发明授权

US06740555B1 Semiconductor structures and manufacturing methods 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06740555B1
公开(公告)日：2004-05-25
申请号：US09408248
申请日：1999-09-29
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Raj Jammy , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L21/28202 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/02238 , H01L21/02247 , H01L21/02255 , H01L21/2822 , H01L21/3144 , H01L21/31658 , H01L27/10864 , H01L29/045 , H01L29/42368 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/7827 , Y10S257/905
摘要： A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the crystallographic plane and another one of such planes being the plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the plane being oxidized at a higher rate than sidewalls in the plane producing silicon dioxide on the silicon nitride layer having thickness over the plane greater than over the plane. The silicon dioxide is subjected to an etch to selectively remove silicon dioxide while leaving substantially un-etched silicon nitride to thereby remove portions of the silicon dioxide over the plane and to thereby expose underlying portions of the silicon nitride material while leaving portions of the silicon dioxide over the plane on underlying portions of the silicon nitride material. Exposed portions of the silicon nitride material are selectively removed to expose underlying portions of the sidewalls of the trench disposed in the plane while leaving substantially un-etched portions of the silicon nitride material disposed on sidewalls of the trench disposed in the plane. The structure is then subjected to an silicon oxidation environment to produce the substantially uniform silicon dioxide layer on the sidewalls of the trench.
摘要翻译：一种用于在独立于轴的硅体上形成基本上均匀的厚的，热生长的二氧化硅材料的方法。沟槽形成在硅体的表面中，这种沟槽具有设置在不同结晶平面内的侧壁，其中一个这样的平面是<100>结晶平面，另外一个这样的平面是<110>平面。在侧壁上形成基本均匀的氮化硅层。具有基本上均匀的氮化硅层的沟槽经受硅氧化环境，其中<110>面中的侧壁以比在100平面中的侧壁更高的速率被氧化，在氮化硅层上产生二氧化硅，厚度大于<100>平面上的厚度。对二氧化硅进行蚀刻以选择性地去除二氧化硅，同时留下基本未蚀刻的氮化硅，从而在<100>平面上除去二氧化硅的一部分，从而暴露氮化硅材料的下面部分，同时留下部分在氮化硅材料的下面部分上的<110>面上的二氧化硅。选择性地去除氮化硅材料的暴露部分以暴露设置在<100>平面中的沟槽的侧壁的下面部分，同时留下设置在设置在<110>平面中的沟槽的侧壁上的氮化硅材料的基本上未蚀刻的部分 >飞机。然后将该结构进行硅氧化环境以在沟槽的侧壁上产生基本均匀的二氧化硅层。

3. 发明授权

US06486024B1 Integrated circuit trench device with a dielectric collar stack, and method of forming thereof 失效
标题翻译：具有介质套管叠层的集成电路沟槽器件及其形成方法
公开(公告)号：US06486024B1
公开(公告)日：2002-11-26
申请号：US09577102
申请日：2000-05-24
申请人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Ulrike Gruening
发明人： Helmut Horst Tews , Alexander Michaelis , Stephan Kudelka , Uwe Schroeder , Ulrike Gruening
IPC分类号： H01L218242
CPC分类号： H01L27/10861
摘要： A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.
摘要翻译：一种使用至少两个绝缘层以形成沟槽器件的隔离套环的方法，以及由其形成的器件。第一层优选是形成在沟槽衬底侧壁上的氧化物（例如，二氧化硅116），并且通过TEOS，LOCOS或组合的TEOS / LOCOS工艺形成。优选地，TEOS工艺和LOCOS工艺都用于形成第一层。第二层优选是形成在氧化物层上的氮化硅层（114）。多层用作沟槽的隔离环叠层。第二层的掺杂剂渗透阻挡性质允许电介质套管叠层用作后续掩埋板（120）掺杂的自对准掩模。

4. 发明授权

US06573137B1 Single sided buried strap 有权
标题翻译：单面埋地带
公开(公告)号：US06573137B1
公开(公告)日：2003-06-03
申请号：US09603442
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Wolfgang Bergner , Gary B. Bronner , Ulrike Gruening , Stephan Kudelka , Alexander Michaelis , Larry Nesbit , Carl J. Radens , Till Schloesser , Helmut Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10864
摘要： A method for clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A barrier material is deposited above a node conductor of the storage capacitor. A layer of silicon is deposited over the barrier material. Dopant ions are implanted at an angle into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.
摘要翻译：一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离环的方法，同时将隔离套环留在深沟槽的其它表面。屏蔽材料沉积在存储电容器的节点导体上方。一层硅沉积在阻挡材料上。掺杂离子以一定角度注入到深沟槽内沉积的硅层中，从而留下沉积的硅沿着深沟槽的一侧被植入。未投影的硅被蚀刻。隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

5. 发明授权

US06372567B1 Control of oxide thickness in vertical transistor structures 有权
标题翻译：垂直晶体管结构中氧化物厚度的控制
公开(公告)号：US06372567B1
公开(公告)日：2002-04-16
申请号：US09553708
申请日：2000-04-20
申请人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening
发明人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening
IPC分类号： H01L218238
CPC分类号： H01L21/28211 , H01L21/2236 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/28238 , H01L27/10864 , H01L27/10873 , H01L29/045
摘要： Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.
摘要翻译：在DRAM中制备垂直晶体管结构的改进方法，其中沟槽顶部氧化物将底部存储电容器与开关晶体管分离，并且其中沟槽的上部在其侧壁处包含垂直晶体管，以获得均匀的栅极氧化沟槽内的所有不同的晶面，使得均匀的厚度与晶体取向无关，包括：a）使晶片沟槽侧壁进行离子轰击足以产生氧化物侧壁的非晶层的时间; 和b）在氧化气氛中加热由步骤（a）得到的晶片，以引起非晶层的氧化和重结晶。

6. 发明授权

US06362040B1 Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates 失效
标题翻译：减少半导体衬底的垂直侧壁的取向依赖氧化
公开(公告)号：US06362040B1
公开(公告)日：2002-03-26
申请号：US09501502
申请日：2000-02-09
申请人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening , Raj Jammy , John Faltermeier
发明人： Helmut Horst Tews , Brian S. Lee , Ulrike Gruening , Raj Jammy , John Faltermeier
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/31662 , H01L27/10876
摘要： A method for growing a dielectric layer on a substrate, in accordance with the present invention, includes the steps of providing a substrate having at least two crystallographic planes which experience different dielectric layer growth rates due to the at least two crystallographic planes. A first dielectric layer is grown on the at least two crystallographic planes such that the first dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness is thicker than the second thickness for the first dielectric layer. Dopants are implanted through the first dielectric layer. A greater number of dopants are implanted in the substrate through the second thickness than through the first thickness of the first dielectric layer. The first dielectric layer is then removed. A second dielectric layer is grown at a same location as the removed first dielectric layer. The second dielectric layer has a first thickness on a first crystallographic plane and a second thickness on a second crystallographic plane. The first thickness and the second thickness of the second dielectric layer are closer in thickness than the first thickness and the second thickness of the first dielectric layer due to the implantation of the dopants.
摘要翻译：根据本发明的用于在衬底上生长电介质层的方法包括以下步骤：提供具有至少两个结晶面的衬底，所述晶体面由于至少两个晶面而具有不同的介电层生长速率。在至少两个晶面上生长第一介电层，使得第一介电层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。第一厚度比第一电介质层的第二厚度厚。通过第一介电层注入掺杂剂。通过第二厚度将更多数量的掺杂剂注入到衬底中，而不是通过第一介电层的第一厚度。然后去除第一介电层。在与去除的第一介电层相同的位置处生长第二介电层。第二电介质层在第一结晶平面上具有第一厚度，在第二结晶平面上具有第二厚度。由于掺杂剂的注入，第二介电层的第一厚度和第二厚度比第一厚度和第一介电层的第二厚度更厚。

7. 发明授权

US06555862B1 Self-aligned buried strap for vertical transistors 有权
标题翻译：用于垂直晶体管的自对准埋地带
公开(公告)号：US06555862B1
公开(公告)日：2003-04-29
申请号：US09670745
申请日：2000-09-27
申请人： Jack A. Mandelman , Ulrike Gruening , Alexander Michaelis
发明人： Jack A. Mandelman , Ulrike Gruening , Alexander Michaelis
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876
摘要： A semiconductor device formed by a method for aligning a strap diffusion, in accordance with the invention, includes the steps of providing a trench in a substrate, the trench having a storage node formed therein including a buried strap on top of the storage node, and depositing a dopant rich material on the buried strap. A trench top dielectric is formed on the dopant rich material, and portions of the dopant rich material are removed above the trench top dielectric. Dopants are outdiffused from the dopant rich material into an adjacent region of the substrate to form the strap diffusion by forming a gate in an upper portion of the trench such that the strap diffusion is operatively disposed relative to the gate.
摘要翻译：通过根据本发明的用于对准带扩散的方法形成的半导体器件包括以下步骤：在衬底中提供沟槽，所述沟槽具有形成在其中的存储节点，所述存储节点包括位于存储节点顶部的掩埋带，以及在掩埋带上沉积富掺杂材料。在富掺杂材料上形成沟槽顶部电介质，并且在沟槽顶部电介质上方去除部分富掺杂材料。通过在沟槽的上部形成栅极以使得带扩散相对于栅极可操作地设置，掺杂剂从掺杂剂富的材料向外扩散到衬底的相邻区域中以形成带扩散。

8. 发明授权

US06429092B1 Collar formation by selective oxide deposition 失效
标题翻译：通过选择性氧化物沉积形成环形
公开(公告)号：US06429092B1
公开(公告)日：2002-08-06
申请号：US09596606
申请日：2000-06-19
申请人： Jochen Beintner , Alexander Michaelis , Ulrike Gruening , Oswald Spindler , Zvonimir Gabric
发明人： Jochen Beintner , Alexander Michaelis , Ulrike Gruening , Oswald Spindler , Zvonimir Gabric
IPC分类号： H01L2176
CPC分类号： H01L27/10861 , H01L21/31612 , H01L21/32 , H01L27/1087
摘要： A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench in a silicon substrate, and depositing and recessing a nitride liner in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar in the trench.
摘要翻译：根据本发明的在沟槽中形成氧化物环的方法包括在硅衬底中形成沟槽，以及在沟槽中沉积和凹陷氮化物衬垫以暴露沟槽侧壁上的硅衬底的一部分。对硅衬底的部分上的氮化物衬垫选择性地沉积氧化物。从氮化物衬垫的表面去除残余氧化物，以在沟槽中形成环。

9. 发明授权

US06762447B1 Field-shield-trench isolation for gigabit DRAMs 有权
标题翻译：用于千兆位DRAM的场屏蔽沟槽隔离
公开(公告)号：US06762447B1
公开(公告)日：2004-07-13
申请号：US09245269
申请日：1999-02-05
申请人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L21/763 , H01L21/765 , H01L27/10829 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.
摘要翻译：形成在半导体主体中的动态随机存取存储器（DRAM）具有通过垂直电隔离沟槽彼此隔离并且与支持电路隔离的各对存储单元。隔离沟槽具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。这使得存储器单元对彼此和从包含在半导体本体内但不位于包围区域内的支撑电路电隔离。隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分，其侧壁部分通过第一电绝缘体至少部分地与沟槽的下部的侧壁分离，并且其具有位于与半导体本体电接触。隔离沟槽的上部填充有第二电绝缘体。

10. 发明授权

US06327170B1 Reducing impact of coupling noise in multi-level bitline architecture 有权
标题翻译：减少耦合噪声对多级位线架构的影响
公开(公告)号：US06327170B1
公开(公告)日：2001-12-04
申请号：US09406890
申请日：1999-09-28
申请人： Gerhard Mueller , Ulrike Gruening
发明人： Gerhard Mueller , Ulrike Gruening
IPC分类号： G11C508
CPC分类号： G11C11/4097
摘要： An integrated circuit comprising first and second bitline pairs 410 and 420 is described. The bitline paths of a bitline pair are on different bitline levels. The bitline paths of the first and second bitline pairs which are on different bitline levels are adjacent to each other. The first bitline pair comprises m vertical-horizontal twists 440, where m is a whole number≧1, and the second bitline pair comprises n vertical-horizontal twists 460 and 461, where n is a whole number≠m. The vertical-horizontal twists transform coupling noise into common mode noise.
摘要翻译：描述了包括第一和第二位线对410和420的集成电路。位线对的位线路径位于不同的位线上。处于不同位线电平的第一和第二位线对的位线路径彼此相邻。第一位线对包括m垂直水平扭转440，其中m是整数> = 1，第二位线对包括n个垂直 - 水平扭转460和461，其中n是整数m。垂直水平扭转将耦合噪声转换为共模噪声。

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