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1. 发明授权

US07482208B2 Thin film transistor array panel and method of manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07482208B2
公开(公告)日：2009-01-27
申请号：US10572234
申请日：2004-09-16
申请人： Sang-Gab Kim , Je-Min Lee , Gwan-Young Cho , Jong-Tae Jeong , In-Ho Song , Hee-Hwan Choe , Sung-Chul Kang , Ho-Min Kang , Beohm-Rock Choi , Joon-Hoo Choi
发明人： Sang-Gab Kim , Je-Min Lee , Gwan-Young Cho , Jong-Tae Jeong , In-Ho Song , Hee-Hwan Choe , Sung-Chul Kang , Ho-Min Kang , Beohm-Rock Choi , Joon-Hoo Choi
IPC分类号： H01L21/00 , H01L21/302
CPC分类号： G02F1/13439 , G02F1/1345 , G02F1/136227 , G02F2001/13629 , H01L27/322 , H01L27/3244 , H01L27/3276 , H01L51/5215 , H01L2251/558
摘要： The present invention relates to a thin film transistor array panel, a liquid crystal display, and a manufacturing method of the same. A TFT array for a LCD or an EL display is used as a circuit board for driving the respective pixels in an independent manner. The present invention provides pixel electrodes and contact assistants, which connect expansions of gate lines and data lines to an external circuit, having a structure of double layers including IZO layer and ITO layer. The ITO layer is disposed on the IZO layer. In the present invention, the pixel electrodes are formed to have double layers of IZO layer and ITO layer to avoid wires from getting damage by the ITO etchant and to prevent prove pins from having accumulation of foreign body during the gross test. In the present invention, the contact assistants may only be formed to have double layers of IZO layer and ITO layer to prevent prove pins from having accumulation of foreign body during the gross test. Since the consumption of ITO is reduced, manufacturing cost decreases.
摘要翻译：本发明涉及薄膜晶体管阵列面板，液晶显示器及其制造方法。用于LCD或EL显示器的TFT阵列用作用于独立地驱动各个像素的电路板。本发明提供了将栅极线和数据线的扩展连接到外部电路的像素电极和接触辅助件，其具有包括IZO层和ITO层的双层结构。 ITO层设置在IZO层上。在本发明中，像素电极形成为具有双层IZO层和ITO层，以避免电线被ITO蚀刻剂损坏，并且防止在总体测试期间引脚不会积累异物。在本发明中，接触助剂只能形成为具有双层IZO层和ITO层，以防止在总体测试期间引脚不会积累异物。由于ITO的消耗减少，制造成本降低。

2. 发明申请

US20100047946A1 THIN FILM ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜阵列及其制造方法
公开(公告)号：US20100047946A1
公开(公告)日：2010-02-25
申请号：US12609568
申请日：2009-10-30
申请人： Sang-Gab Kim , Sung-Chul Kang , Ho-Min Kang , In-Ho Song , Hee-Hwan Choe
发明人： Sang-Gab Kim , Sung-Chul Kang , Ho-Min Kang , In-Ho Song , Hee-Hwan Choe
IPC分类号： H01L21/28
CPC分类号： H01L27/1259 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L27/1214 , H01L27/124 , H01L27/1288 , H01L27/3262
摘要： A method of manufacturing a thin film array panel is provided, which includes: forming a gate line formed on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode disposed at least on the ohmic contact layer, forming an oxide on the data line; etching the ohmic contact layer using the data line and the drain electrode as an etch mask; and forming a pixel electrode connected to the drain electrode.
摘要翻译：提供一种制造薄膜阵列面板的方法，其包括：形成在基底上的栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在所述半导体层上形成欧姆接触层; 形成至少设置在所述欧姆接触层上的数据线和漏电极，在所述数据线上形成氧化物; 使用数据线和漏电极作为蚀刻掩模蚀刻欧姆接触层; 以及形成连接到所述漏电极的像素电极。

3. 发明授权

US08093595B2 Thin film array panel and manufacturing method thereof 有权
标题翻译：薄膜阵列面板及其制造方法
公开(公告)号：US08093595B2
公开(公告)日：2012-01-10
申请号：US12609568
申请日：2009-10-30
申请人： Sang-Gab Kim , Sung-Chul Kang , Ho-Min Kang , In-Ho Song , Hee-Hwan Choe
发明人： Sang-Gab Kim , Sung-Chul Kang , Ho-Min Kang , In-Ho Song , Hee-Hwan Choe
IPC分类号： H01L29/04
CPC分类号： H01L27/1259 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L27/1214 , H01L27/124 , H01L27/1288 , H01L27/3262
摘要： A method of manufacturing a thin film array panel is provided, which includes: forming a gate line formed on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode disposed at least on the ohmic contact layer, forming an oxide on the data line; etching the ohmic contact layer using the data line and the drain electrode as an etch mask; and forming a pixel electrode connected to the drain electrode.
摘要翻译：提供一种制造薄膜阵列面板的方法，其包括：形成在基底上的栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在所述半导体层上形成欧姆接触层; 形成至少设置在所述欧姆接触层上的数据线和漏电极，在所述数据线上形成氧化物; 使用数据线和漏电极作为蚀刻掩模蚀刻欧姆接触层; 以及形成连接到所述漏电极的像素电极。

4. 发明授权

US07619249B2 Thin film array panel and manufacturing method thereof 失效
标题翻译：薄膜阵列面板及其制造方法
公开(公告)号：US07619249B2
公开(公告)日：2009-11-17
申请号：US10878529
申请日：2004-06-29
申请人： Sang-Gab Kim , Sung-Chul Kang , Ho-Min Kang , In-Ho Song , Hee-Hwan Choe
发明人： Sang-Gab Kim , Sung-Chul Kang , Ho-Min Kang , In-Ho Song , Hee-Hwan Choe
IPC分类号： H01L29/04
CPC分类号： H01L27/1259 , G02F1/136227 , G02F1/1368 , G02F2001/13629 , H01L27/1214 , H01L27/124 , H01L27/1288 , H01L27/3262
摘要： A method of manufacturing a thin film array panel is provided, which includes: forming a gate line formed on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode disposed at least on the ohmic contact layer; forming an oxide on the data line; etching the ohmic contact layer using the data line and the drain electrode as an etch mask; and forming a pixel electrode connected to the drain electrode.
摘要翻译：提供一种制造薄膜阵列面板的方法，其包括：形成在基底上的栅极线; 在栅极线上形成栅极绝缘层; 在所述栅极绝缘层上形成半导体层; 在所述半导体层上形成欧姆接触层; 形成至少设置在所述欧姆接触层上的数据线和漏电极; 在数据线上形成氧化物; 使用数据线和漏电极作为蚀刻掩模蚀刻欧姆接触层; 以及形成连接到所述漏电极的像素电极。

5. 发明申请

US20070065991A1 Thin film transistor array panel and method of manufacturing the same 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20070065991A1
公开(公告)日：2007-03-22
申请号：US10572234
申请日：2004-09-16
申请人： Sang-Gab Kim , Je-Min Lee , Gwan-Young Cho , Jong-Tae Jeong , In-Ho Song , Hee-Hwan Choe , Sung-Chul Kang , Ho-Min Kang , Beohm-Rock Choi , Joon-Hoo Choi
发明人： Sang-Gab Kim , Je-Min Lee , Gwan-Young Cho , Jong-Tae Jeong , In-Ho Song , Hee-Hwan Choe , Sung-Chul Kang , Ho-Min Kang , Beohm-Rock Choi , Joon-Hoo Choi
IPC分类号： H01L21/84 , H01L21/00 , H01L31/00 , G02F1/1343
CPC分类号： G02F1/13439 , G02F1/1345 , G02F1/136227 , G02F2001/13629 , H01L27/322 , H01L27/3244 , H01L27/3276 , H01L51/5215 , H01L2251/558
摘要： The present invention relates to a thin film transistor array panel, a liquid crystal display, and a manufacturing method of the same. A TFT array for a LCD or an EL display is used as a circuit board for driving the respective pixels in an independent manner. The present invention provides pixel electrodes and contact assistants, which connect expansions of gate lines and data lines to an external circuit, having a structure of double layers including IZO layer and ITO layer. The ITO layer is disposed on the IZO layer. In the present invention, the pixel electrodes are formed to have double layers of IZO layer and ITO layer to avoid wires from getting damage by the ITO etchant and to prevent prove pins from having accumulation of foreign body during the gross test. In the present invention, the contact assistants may only be formed to have double layers of IZO layer and ITO layer to prevent prove pins from having accumulation of foreign body during the gross test. Since the consumption of ITO is reduced, manufacturing cost decreases.
摘要翻译：本发明涉及薄膜晶体管阵列面板，液晶显示器及其制造方法。用于LCD或EL显示器的TFT阵列用作用于独立地驱动各个像素的电路板。本发明提供了将栅极线和数据线的扩展连接到外部电路的像素电极和接触辅助件，其具有包括IZO层和ITO层的双层结构。 ITO层设置在IZO层上。在本发明中，像素电极形成为具有双层IZO层和ITO层，以避免电线被ITO蚀刻剂损坏，并且防止在总体测试期间引脚不会积累异物。在本发明中，接触助剂只能形成为具有双层IZO层和ITO层，以防止在总体测试期间引脚不会积累异物。由于ITO的消耗减少，制造成本降低。

6. 发明申请

US20050016568A1 Apparatus and method for cleaning of semiconductor device manufacturing equipment 审中-公开
标题翻译：用于清洁半导体器件制造设备的装置和方法
公开(公告)号：US20050016568A1
公开(公告)日：2005-01-27
申请号：US10870309
申请日：2004-06-16
申请人： Hee-Hwan Choe , In-Ho Song , Sung-Chul Kang , Sang-Gab Kim
发明人： Hee-Hwan Choe , In-Ho Song , Sung-Chul Kang , Sang-Gab Kim
IPC分类号： B08B7/00 , C23C16/44 , H01J37/32 , H01L21/00 , H01L21/203 , H01L21/205 , H01L21/3065 , B08B3/00
CPC分类号： H01L21/67069 , B08B7/0035 , C23C16/4405 , H01J37/32568 , H01J37/32862
摘要： A cleaning apparatus and method are provided for the removal of contaminants from semiconductor processing equipment. An electrode to generate a cleaning plasma is provided within a processing chamber and a guide system is capable of moving the electrode over contaminated areas. Advantageously, the present invention saves cleaning time compared with a conventional cleaning method that requires the opening and cleaning of the chamber and also allows for increasing the interval between regular cleanings.
摘要翻译：提供了一种用于从半导体加工设备去除污染物的清洁设备和方法。在处理室内设置有用于产生清洗等离子体的电极，并且引导系统能够将电极移动到污染区域上。有利地，与需要打开和清洁室的常规清洁方法相比，本发明节省了清洁时间，并且还允许增加常规清洁之间的间隔。

7. 发明申请

US20080090343A1 METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL 审中-公开
标题翻译：制造薄膜晶体管阵列的方法
公开(公告)号：US20080090343A1
公开(公告)日：2008-04-17
申请号：US11752948
申请日：2007-05-24
申请人： In-Ho Song , Won Song , Sang-Gab Kim
发明人： In-Ho Song , Won Song , Sang-Gab Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/1288 , H01L27/124 , H01L29/458
摘要： A method of manufacturing a thin film transistor array panel includes forming a gate line on a substrate; sequentially forming a gate insulating layer, a semiconductor layer, and a conductive layer on the gate line; forming a photosensitive film on the conductive layer; forming a first photosensitive film pattern including a first region and a second region having a lesser thickness than the first region by patterning the photosensitive film; forming a data pattern by etching the conductive layer using the first photosensitive film pattern as a mask; forming a second photosensitive film pattern by ashing the first photosensitive film pattern to partially remove the first photosensitive film; forming a semiconductor pattern by etching the semiconductor layer using the second photosensitive film pattern as a mask; and forming a source and drain electrode by etching the data pattern exposed in the second region of the second photosensitive film pattern.
摘要翻译：制造薄膜晶体管阵列面板的方法包括在基板上形成栅极线; 在栅极线上依次形成栅绝缘层，半导体层和导电层; 在导电层上形成感光膜; 通过图案化所述感光膜，形成包括具有比所述第一区域更薄的厚度的第一区域和第二区域的第一感光膜图案; 通过使用第一感光膜图案作为掩模蚀刻导电层来形成数据图案; 通过灰化所述第一感光膜图案以部分地除去所述第一感光膜来形成第二感光膜图案; 通过使用第二感光膜图案作为掩模蚀刻半导体层来形成半导体图案; 以及通过蚀刻在第二感光膜图案的第二区域中暴露的数据图案来形成源电极和漏电极。

8. 发明授权

US07466026B2 Passivation layer assembly on a substrate and display substrate having the same 有权
标题翻译：钝化层组件在基板上和具有该钝化层组件的显示基板上
公开(公告)号：US07466026B2
公开(公告)日：2008-12-16
申请号：US11239716
申请日：2005-09-29
申请人： In-Ho Song , Kwan-young Cho , Ho Lee , Je-Min Lee
发明人： In-Ho Song , Kwan-young Cho , Ho Lee , Je-Min Lee
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L29/458 , G02F1/136227 , H01L27/1244 , H01L27/1248
摘要： A passivation layer assembly and a display substrate having the same are presented. The passivation layer assembly is positioned on a substrate having a thin film assembly and protects the thin film assembly. The thin film assembly includes a first passivation layer and a second passivation layer. The first passivation layer contacts the thin film assembly. The first passivation layer has a first etching rate with respect to an etching agent. The second passivation layer is on the first passivation layer. The second passivation layer has a second etching rate that is higher than the first etching rate with respect to the etching agent. The passivation assembly decrease the malfunction rate of the display device.
摘要翻译：提出了一种钝化层组件及其显示基板。钝化层组件定位在具有薄膜组件的基底上，并保护薄膜组件。薄膜组件包括第一钝化层和第二钝化层。第一钝化层接触薄膜组件。第一钝化层相对于蚀刻剂具有第一蚀刻速率。第二钝化层位于第一钝化层上。第二钝化层具有相对于蚀刻剂高于第一蚀刻速率的第二蚀刻速率。钝化组件降低了显示设备的故障率。

9. 发明申请

US20060076653A1 Passivation layer assembly on a substrate and display substrate having the same 有权
标题翻译：钝化层组件在基板上和具有该钝化层组件的显示基板上
公开(公告)号：US20060076653A1
公开(公告)日：2006-04-13
申请号：US11239716
申请日：2005-09-29
申请人： In-Ho Song , Kwan-young Cho , Ho Lee , Je-Min Lee
发明人： In-Ho Song , Kwan-young Cho , Ho Lee , Je-Min Lee
IPC分类号： H01L23/58
CPC分类号： H01L29/458 , G02F1/136227 , H01L27/1244 , H01L27/1248
摘要： A passivation layer assembly and a display substrate having the same are presented. The passivation layer assembly is positioned on a substrate having a thin film assembly and protects the thin film assembly. The thin film assembly includes a first passivation layer and a second passivation layer. The first passivation layer contacts the thin film assembly. The first passivation layer has a first etching rate with respect to an etching agent. The second passivation layer is on the first passivation layer. The second passivation layer has a second etching rate that is higher than the first etching rate with respect to the etching agent. The passivation assembly decrease the malfunction rate of the display device.
摘要翻译：提出了一种钝化层组件及其显示基板。钝化层组件定位在具有薄膜组件的基底上，并保护薄膜组件。薄膜组件包括第一钝化层和第二钝化层。第一钝化层接触薄膜组件。第一钝化层相对于蚀刻剂具有第一蚀刻速率。第二钝化层位于第一钝化层上。第二钝化层具有相对于蚀刻剂高于第一蚀刻速率的第二蚀刻速率。钝化组件降低显示设备的故障率。

10. 发明申请

US20060118049A1 Vacuum-generating apparatus and thin film processing apparatus having the same 审中-公开
标题翻译：真空发生装置和具有该真空发生装置的薄膜处理装置
公开(公告)号：US20060118049A1
公开(公告)日：2006-06-08
申请号：US11261961
申请日：2005-10-28
申请人： In-Ho Song , Kwan-Young Cho
发明人： In-Ho Song , Kwan-Young Cho
IPC分类号： H01L21/306 , C23C16/00
CPC分类号： F04D29/701 , C23C16/4412 , F04D17/168 , F04D19/04
摘要： A vacuum-generating apparatus includes a vacuum-generating unit and a stabilizing module. The vacuum-generating unit exhausts a fluid from a processing area to generate a vacuum pressure in the processing area. The stabilizing module is disposed between the processing area and the vacuum-generating unit, and the stabilizing module includes at least two curved fluid paths through which the fluid passes. The fluid is exhausted from the processing area through the curved fluid paths, to thereby improve uniformity of the vacuum pressure in the processing area.
摘要翻译：真空发生装置包括真空发生单元和稳定模块。真空发生单元从处理区域排出流体，以在处理区域中产生真空压力。稳定模块设置在处理区域和真空发生单元之间，并且稳定模块包括流体通过的至少两个弯曲流体路径。流体通过弯曲的流体路径从处理区域排出，从而提高处理区域中的真空压力的均匀性。

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