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1. 发明授权

US6040729A Digital output buffer for multiple voltage system 失效
标题翻译：用于多电压系统的数字输出缓冲器
公开(公告)号：US6040729A
公开(公告)日：2000-03-21
申请号：US917306
申请日：1997-08-25
申请人： Hector Sanchez , Jose M. Alvarez , Joshua Siegel , Carmine Nicoletta
发明人： Hector Sanchez , Jose M. Alvarez , Joshua Siegel , Carmine Nicoletta
IPC分类号： H03K19/003 , H03K17/687
CPC分类号： H03K19/00384 , H03K19/00315
摘要： An output buffer translates digital input signals which toggle between ground and V.sub.DDL to signals which toggle between ground and V.sub.DDH. The technology dielectric breakdown voltage limit is less than the magnitude of V.sub.DDH, such that use of a traditional output stage would subject transistors' dielectrics to voltages which exceed their dielectric breakdown limit, and would thus be damaged. Predrive circuits (40, 50) control output stage (70) transistors' (72, 78) gates, and voltage dropping circuits control output stage (70) transistors (74, 76). These control signals are generated specifically to maximize output stage transistor drive strengths, thereby minimizing output stage size. Output buffer functions when V.sub.DDL =V.sub.DDH, and its performance is V.sub.DDL independent. Temperature compensation is incorporated into the output buffer by deliberately offsetting temperature effects on output stage transistor drive strengths. Desired performance and temperature compensation are accomplished without subjecting any dielectrics to voltages which exceed the technology dielectric breakdown limit.
摘要翻译：输出缓冲器将数字输入信号转换为在地和VDDL之间切换的接地和VDDH之间的信号。技术介电击穿电压极限小于VDDH的大小，因此使用传统的输出级将使晶体管的电介质受到超过其介电击穿极限的电压，从而将被损坏。预驱动电路（40,50）控制输出级（70）晶体管（72,78）门，并且降压电路控制输出级（70）晶体管（74,76）。专门生成这些控制信号以使输出级晶体管驱动强度最大化，从而使输出级大小最小化。 VDDL = VDDH时的输出缓冲器功能，其性能与VDDL无关。温度补偿通过故意抵消输出级晶体管驱动强度的温度影响而被并入输出缓冲器。实现所需的性能和温度补偿，而不会对任何电介质施加超过技术介电击穿极限的电压。

2. 发明授权

US5917358A Method and output buffer with programmable bias to accommodate multiple supply voltages 失效
标题翻译：具有可编程偏置的方法和输出缓冲器，以适应多种电源电压
公开(公告)号：US5917358A
公开(公告)日：1999-06-29
申请号：US987361
申请日：1997-12-09
申请人： Hector Sanchez , Carmine Nicoletta , Joshua Siegel , Jose Alvarez
发明人： Hector Sanchez , Carmine Nicoletta , Joshua Siegel , Jose Alvarez
IPC分类号： H03K19/0185 , H03L5/00
CPC分类号： H03K19/018585
摘要： Output buffer (100) translates input signals from one voltage range to a second voltage range. The second voltage range may be identical to the first range or may be greater. The particular range is programmable by one of several ways. This feature makes output buffer especially suitable for use in devices which must be compatible with two voltage ranges. Output buffer uses a bias generator (110) to limit the voltage across the gate oxide of its various transistors to a level which is consistent with the first voltage range.
摘要翻译：输出缓冲器（100）将输入信号从一个电压范围转换到第二电压范围。第二电压范围可以与第一范围相同或者可以更大。特定范围可以通过几种方式之一进行编程。该功能使输出缓冲器特别适用于必须兼容两个电压范围的器件。输出缓冲器使用偏置发生器（110）将其各种晶体管的栅极氧化物上的电压限制到与第一电压范围一致的水平。

3. 发明授权

US5742799A Method and apparatus for synchronizing multiple clocks 失效
标题翻译：用于同步多个时钟的方法和装置
公开(公告)号：US5742799A
公开(公告)日：1998-04-21
申请号：US801648
申请日：1997-02-18
申请人： Michael Alexander , Carmine Nicoletta , Arthur R. Piejko
发明人： Michael Alexander , Carmine Nicoletta , Arthur R. Piejko
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A method and apparatus for synchronizing multiple busses having different cycle times in a data processing system (10). The present invention synchronizes multiple clocks having different phase and frequencies without redundant use of phase lock loop units. An initial unit (7) receives an external system clock having an initial phase and frequency. An internal clock (112) is generated which is a phase and frequency adjusted derivation of the system clock. From this internal clock (112) a global clock (101) for use within the data processor (10) is generated. A second unit (9) receives the internal clock (112) and performs phase adjustment to provide a peripheral clock (114). The provision of the internal clock (112) detaches the dependency of peripheral clock (114) generation from the global clock (101), while maintaining a phase relationship with the global clock (101). In one embodiment, the present invention is implemented without the costly use of multiple phase lock loops.
摘要翻译：一种用于在数据处理系统（10）中同步具有不同周期时间的多个总线的方法和装置。本发明使具有不同相位和频率的多个时钟同步，而不需要冗余地使用锁相环单元。初始单元（7）接收具有初始相位和频率的外部系统时钟。产生内部时钟（112），其是系统时钟的相位和频率调整推导。从该内部时钟（112）产生用于数据处理器（10）内的全局时钟（101）。第二单元（9）接收内部时钟（112）并执行相位调整以提供外设时钟（114）。在保持与全局时钟（101）的相位关系的同时，内部时钟（112）的提供将外围时钟（114）产生的依赖性与全局时钟（101）分离。在一个实施例中，实现本发明，而不需要昂贵地使用多个锁相环。

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